Searched refs:cr0 (Results 1 – 5 of 5) sorted by relevance
| /Zephyr-latest/arch/x86/core/ |
| D | cache.c | 33 unsigned long cr0 = 0; in arch_dcache_enable() local
39 : "=r" (cr0) in arch_dcache_enable()
45 unsigned long cr0 = 0; in arch_dcache_disable() local
52 : "=r" (cr0) in arch_dcache_disable()
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| /Zephyr-latest/arch/x86/core/ia32/ |
| D | crt0.S | 88 movl %cr0, %eax
90 movl %eax, %cr0
111 movl %cr0, %eax
113 movl %eax, %cr0
152 movl %cr0, %eax /* move CR0 to EAX */
154 movl %eax, %cr0 /* move EAX to CR0 */
163 movl %cr0, %eax /* move CR0 to EAX */
166 movl %eax, %cr0 /* move EAX to CR0 */
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| D | swap.S | 294 movl %cr0, %edx
296 movl %edx, %cr0
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| /Zephyr-latest/drivers/spi/ |
| D | spi_pl022.c | 350 uint32_t cr0; in spi_pl022_configure() local
399 cr0 = 0; in spi_pl022_configure()
400 cr0 |= (postdiv << SSP_CR0_SCR_LSB); in spi_pl022_configure()
401 cr0 |= (SPI_WORD_SIZE_GET(op) - 1); in spi_pl022_configure()
402 cr0 |= (op & SPI_MODE_CPOL) ? SSP_CR0_MASK_SPO : 0; in spi_pl022_configure()
403 cr0 |= (op & SPI_MODE_CPHA) ? SSP_CR0_MASK_SPH : 0; in spi_pl022_configure()
410 SSP_WRITE_REG(SSP_CR0(cfg->reg), cr0); in spi_pl022_configure()
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| /Zephyr-latest/arch/x86/core/intel64/ |
| D | locore.S | 52 movl %cr0, %eax
54 movl %eax, %cr0
74 movq %cr0, %rax
80 movq %rax, %cr0
134 movl %cr0, %eax
136 movl %eax, %cr0
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