Searched refs:clock_ctrl (Results 1 – 2 of 2) sorted by relevance
187 regs->clock_ctrl &= ~EMMC_HOST_INTERNAL_CLOCK_EN; in emmc_disable_clock()188 regs->clock_ctrl &= ~EMMC_HOST_SD_CLOCK_EN; in emmc_disable_clock()190 while ((regs->clock_ctrl & EMMC_HOST_SD_CLOCK_EN) != 0) { in emmc_disable_clock()201 regs->clock_ctrl |= EMMC_HOST_INTERNAL_CLOCK_EN; in emmc_enable_clock()203 while ((regs->clock_ctrl & EMMC_HOST_INTERNAL_CLOCK_STABLE) == 0) { in emmc_enable_clock()208 regs->clock_ctrl |= EMMC_HOST_SD_CLOCK_EN; in emmc_enable_clock()209 while ((regs->clock_ctrl & EMMC_HOST_SD_CLOCK_EN) == 0) { in emmc_enable_clock()262 SET_BITS(regs->clock_ctrl, EMMC_HOST_CLK_SDCLCK_FREQ_SEL_LOC, in emmc_clock_set()264 SET_BITS(regs->clock_ctrl, EMMC_HOST_CLK_SDCLCK_FREQ_SEL_UPPER_LOC, in emmc_clock_set()
206 volatile uint16_t clock_ctrl; /**< Clock Control */ member
