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Searched refs:clk_info_table_size (Results 1 – 4 of 4) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_control_r8a779f0_cpg_mssr.c271 .cmn.clk_info_table_size[CPG_CORE] = ARRAY_SIZE(core_props), \
273 .cmn.clk_info_table_size[CPG_MOD] = ARRAY_SIZE(mod_props), \
Dclock_control_renesas_cpg_mssr.h38 const uint32_t clk_info_table_size[CPG_NUM_DOMAINS]; member
Dclock_control_r8a7795_cpg_mssr.c280 .cmn.clk_info_table_size[CPG_CORE] = ARRAY_SIZE(core_props), \
282 .cmn.clk_info_table_size[CPG_MOD] = ARRAY_SIZE(mod_props), \
Dclock_control_renesas_cpg_mssr.c78 uint32_t table_size = data->clk_info_table_size[domain]; in rcar_cpg_find_clk_info_by_module_id()
356 for (idx = 0; idx < data->clk_info_table_size[domain]; idx++, item++) { in rcar_cpg_build_clock_relationship()
415 for (idx = 0; idx < data->clk_info_table_size[domain]; idx++, item++) { in rcar_cpg_update_all_in_out_freq()