Searched refs:checksum_status (Results 1 – 2 of 2) sorted by relevance
470 uint32_t checksum_status = current_descriptor->app2; in dma_xilinx_axi_dma_clean_up_sg_descriptors() local472 if (checksum_status & XILINX_AXI_DMA_SG_DESCRIPTOR_APP2_FCS_ERR_MASK) { in dma_xilinx_axi_dma_clean_up_sg_descriptors()474 checksum_status); in dma_xilinx_axi_dma_clean_up_sg_descriptors()478 if ((checksum_status & XILINX_AXI_DMA_SG_DESCRIPTOR_APP2_IP_ERR_MASK) == in dma_xilinx_axi_dma_clean_up_sg_descriptors()481 checksum_status); in dma_xilinx_axi_dma_clean_up_sg_descriptors()485 if ((checksum_status & XILINX_AXI_DMA_SG_DESCRIPTOR_APP2_UDP_ERR_MASK) == in dma_xilinx_axi_dma_clean_up_sg_descriptors()488 checksum_status); in dma_xilinx_axi_dma_clean_up_sg_descriptors()492 if ((checksum_status & XILINX_AXI_DMA_SG_DESCRIPTOR_APP2_TCP_ERR_MASK) == in dma_xilinx_axi_dma_clean_up_sg_descriptors()495 checksum_status); in dma_xilinx_axi_dma_clean_up_sg_descriptors()
85 uint16_t checksum_status; in phy_dm8806_write_reg() local127 DM8806_SMI_BUS_ERR_CHK_REG_ADDRESS, &checksum_status); in phy_dm8806_write_reg()137 checksum_mismatch = (bool)(checksum_status & BIT(DM8806_SMI_ERR)); in phy_dm8806_write_reg()
