Searched refs:chan_mask (Results 1 – 4 of 4) sorted by relevance
30 uint8_t chan_mask; member92 res = tca954x_set_channel(down_cfg->root, down_cfg->chan_mask); in tca954x_transfer()147 if ((chan_cfg->chan_mask >= BIT(root_cfg->nchans) && !chan_cfg->has_enable) || in tca954x_channel_init()148 (chan_cfg->chan_mask > (BIT(2) | (root_cfg->nchans - 1)) && chan_cfg->has_enable)) { in tca954x_channel_init()170 .chan_mask = has_enable_bit ? BIT(2) | DT_REG_ADDR(node_id) \
41 uint32_t chan_mask; in adc_kb1200_validate_buffer_size() local43 for (chan_mask = 0x80; chan_mask != 0; chan_mask >>= 1) { in adc_kb1200_validate_buffer_size()44 if (chan_mask & sequence->channels) { in adc_kb1200_validate_buffer_size()
181 uint32_t chan_mask; in adc_xec_validate_buffer_size() local183 for (chan_mask = 0x80; chan_mask != 0; chan_mask >>= 1) { in adc_xec_validate_buffer_size()184 if (chan_mask & sequence->channels) { in adc_xec_validate_buffer_size()
213 const uint32_t chan_mask = BIT(config->channel); in gpio_xlnx_axi_pin_interrupt_configure() local245 if (!(enabled_interrupts & chan_mask)) { in gpio_xlnx_axi_pin_interrupt_configure()249 if (sys_read32(config->base + IPISR_OFFSET) & chan_mask) { in gpio_xlnx_axi_pin_interrupt_configure()250 sys_write32(chan_mask, config->base + IPISR_OFFSET); in gpio_xlnx_axi_pin_interrupt_configure()254 enabled_interrupts |= chan_mask; in gpio_xlnx_axi_pin_interrupt_configure()257 enabled_interrupts &= ~chan_mask; in gpio_xlnx_axi_pin_interrupt_configure()285 const uint32_t chan_mask = BIT(config->channel); in gpio_xlnx_axi_get_pending_int() local299 if (!(interrupt_flags & chan_mask)) { in gpio_xlnx_axi_get_pending_int()305 sys_write32(chan_mask, config->base + IPISR_OFFSET); in gpio_xlnx_axi_get_pending_int()
