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Searched refs:bdf (Results 1 – 25 of 38) sorted by relevance

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/Zephyr-latest/drivers/pcie/host/
Dcontroller.c20 uint32_t pcie_conf_read(pcie_bdf_t bdf, unsigned int reg) in pcie_conf_read() argument
30 return pcie_ctrl_conf_read(dev, bdf, reg); in pcie_conf_read()
33 void pcie_conf_write(pcie_bdf_t bdf, unsigned int reg, uint32_t data) in pcie_conf_write() argument
43 pcie_ctrl_conf_write(dev, bdf, reg, data); in pcie_conf_write()
46 uint32_t pcie_generic_ctrl_conf_read(mm_reg_t cfg_addr, pcie_bdf_t bdf, unsigned int reg) in pcie_generic_ctrl_conf_read() argument
48 volatile uint32_t *bdf_cfg_mem = (volatile uint32_t *)((uintptr_t)cfg_addr + (bdf << 4)); in pcie_generic_ctrl_conf_read()
57 void pcie_generic_ctrl_conf_write(mm_reg_t cfg_addr, pcie_bdf_t bdf, in pcie_generic_ctrl_conf_write() argument
60 volatile uint32_t *bdf_cfg_mem = (volatile uint32_t *)((uintptr_t)cfg_addr + (bdf << 4)); in pcie_generic_ctrl_conf_write()
69 static void pcie_generic_ctrl_enumerate_bars(const struct device *ctrl_dev, pcie_bdf_t bdf, in pcie_generic_ctrl_enumerate_bars() argument
80 data = scratch = pcie_conf_read(bdf, reg); in pcie_generic_ctrl_enumerate_bars()
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Dpcie.c40 void pcie_set_cmd(pcie_bdf_t bdf, uint32_t bits, bool on) in pcie_set_cmd() argument
44 cmdstat = pcie_conf_read(bdf, PCIE_CONF_CMDSTAT); in pcie_set_cmd()
52 pcie_conf_write(bdf, PCIE_CONF_CMDSTAT, cmdstat); in pcie_set_cmd()
55 uint32_t pcie_get_cap(pcie_bdf_t bdf, uint32_t cap_id) in pcie_get_cap() argument
60 data = pcie_conf_read(bdf, PCIE_CONF_CMDSTAT); in pcie_get_cap()
62 data = pcie_conf_read(bdf, PCIE_CONF_CAPPTR); in pcie_get_cap()
67 data = pcie_conf_read(bdf, reg); in pcie_get_cap()
79 uint32_t pcie_get_ext_cap(pcie_bdf_t bdf, uint32_t cap_id) in pcie_get_ext_cap() argument
85 data = pcie_conf_read(bdf, reg); in pcie_get_ext_cap()
113 static bool pcie_get_bar(pcie_bdf_t bdf, in pcie_get_bar() argument
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Dmsi.c13 static uint32_t pcie_msi_base(pcie_bdf_t bdf, bool *msi) in pcie_msi_base() argument
21 base = pcie_get_cap(bdf, PCI_CAP_ID_MSI); in pcie_msi_base()
26 base_msix = pcie_get_cap(bdf, PCI_CAP_ID_MSIX); in pcie_msi_base()
70 static uint32_t get_msix_table_size(pcie_bdf_t bdf, in get_msix_table_size() argument
75 mcr = pcie_conf_read(bdf, base + PCIE_MSIX_MCR); in get_msix_table_size()
80 static bool map_msix_table_entries(pcie_bdf_t bdf, in map_msix_table_entries() argument
91 table_offset = pcie_conf_read(bdf, base + PCIE_MSIX_TR); in map_msix_table_entries()
95 if (!pcie_get_mbar(bdf, table_bir, &bar)) { in map_msix_table_entries()
128 static uint32_t get_msi_mmc(pcie_bdf_t bdf, in get_msi_mmc() argument
133 mcr = pcie_conf_read(bdf, base + PCIE_MSI_MCR); in get_msi_mmc()
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Dvc.c14 uint32_t pcie_vc_cap_lookup(pcie_bdf_t bdf, struct pcie_vc_regs *regs) in pcie_vc_cap_lookup() argument
18 base = pcie_get_ext_cap(bdf, PCIE_EXT_CAP_ID_VC); in pcie_vc_cap_lookup()
20 base = pcie_get_ext_cap(bdf, PCIE_EXT_CAP_ID_MFVC_VC); in pcie_vc_cap_lookup()
26 regs->cap_reg_1.raw = pcie_conf_read(bdf, base + in pcie_vc_cap_lookup()
28 regs->cap_reg_2.raw = pcie_conf_read(bdf, base + in pcie_vc_cap_lookup()
30 regs->ctrl_reg.raw = pcie_conf_read(bdf, base + in pcie_vc_cap_lookup()
36 void pcie_vc_load_resources_regs(pcie_bdf_t bdf, in pcie_vc_load_resources_regs() argument
45 pcie_conf_read(bdf, base + in pcie_vc_load_resources_regs()
48 pcie_conf_read(bdf, base + in pcie_vc_load_resources_regs()
51 pcie_conf_read(bdf, base + in pcie_vc_load_resources_regs()
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Dshell.c93 static void show_msi(const struct shell *sh, pcie_bdf_t bdf) in show_msi() argument
99 msi = pcie_get_cap(bdf, PCI_CAP_ID_MSI); in show_msi()
102 data = pcie_conf_read(bdf, msi + PCIE_MSI_MCR); in show_msi()
109 msi = pcie_get_cap(bdf, PCI_CAP_ID_MSIX); in show_msi()
115 data = pcie_conf_read(bdf, msi + PCIE_MSIX_MCR); in show_msi()
126 offset = pcie_conf_read(bdf, msi + PCIE_MSIX_TR); in show_msi()
134 offset = pcie_conf_read(bdf, msi + PCIE_MSIX_PBA); in show_msi()
145 static void show_bars(const struct shell *sh, pcie_bdf_t bdf) in show_bars() argument
151 data = pcie_conf_read(bdf, bar); in show_bars()
166 pcie_conf_read(bdf, bar)); in show_bars()
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Dptm.c30 cap.raw = pcie_conf_read(config->pcie->bdf, base + PTM_CAP_REG_OFFSET); in pcie_ptm_root_setup()
32 LOG_ERR("PTM root not supported on 0x%x", config->pcie->bdf); in pcie_ptm_root_setup()
39 pcie_conf_write(config->pcie->bdf, base + PTM_CTRL_REG_OFFSET, ctrl.raw); in pcie_ptm_root_setup()
41 LOG_DBG("PTM root 0x%x enabled", config->pcie->bdf); in pcie_ptm_root_setup()
51 reg = pcie_get_ext_cap(config->pcie->bdf, PCIE_EXT_CAP_ID_PTM); in pcie_ptm_root_init()
53 LOG_ERR("PTM capability not exposed on 0x%x", config->pcie->bdf); in pcie_ptm_root_init()
72 bool pcie_ptm_enable(pcie_bdf_t bdf) in DT_INST_FOREACH_STATUS_OKAY()
78 base = pcie_get_ext_cap(bdf, PCIE_EXT_CAP_ID_PTM); in DT_INST_FOREACH_STATUS_OKAY()
80 LOG_ERR("PTM capability not exposed on 0x%x", bdf); in DT_INST_FOREACH_STATUS_OKAY()
84 cap.raw = pcie_conf_read(bdf, base + PTM_CAP_REG_OFFSET); in DT_INST_FOREACH_STATUS_OKAY()
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Dpcie_ecam.c179 static uint32_t pcie_ecam_ctrl_conf_read(const struct device *dev, pcie_bdf_t bdf, unsigned int reg) in pcie_ecam_ctrl_conf_read() argument
183 return pcie_generic_ctrl_conf_read(data->cfg_addr, bdf, reg); in pcie_ecam_ctrl_conf_read()
186 static void pcie_ecam_ctrl_conf_write(const struct device *dev, pcie_bdf_t bdf, unsigned int reg, in pcie_ecam_ctrl_conf_write() argument
191 pcie_generic_ctrl_conf_write(data->cfg_addr, bdf, reg, reg_data); in pcie_ecam_ctrl_conf_write()
194 static bool pcie_ecam_region_allocate_type(struct pcie_ecam_data *data, pcie_bdf_t bdf, in pcie_ecam_region_allocate_type() argument
213 static bool pcie_ecam_region_allocate(const struct device *dev, pcie_bdf_t bdf, in pcie_ecam_region_allocate() argument
222 LOG_DBG("bdf %x no mem region defined for allocation", bdf); in pcie_ecam_region_allocate()
227 LOG_DBG("bdf %x no io region defined for allocation", bdf); in pcie_ecam_region_allocate()
247 return pcie_ecam_region_allocate_type(data, bdf, bar_size, bar_bus_addr, type); in pcie_ecam_region_allocate()
250 static bool pcie_ecam_region_get_allocate_base(const struct device *dev, pcie_bdf_t bdf, in pcie_ecam_region_get_allocate_base() argument
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Dvc.h121 uint32_t pcie_vc_cap_lookup(pcie_bdf_t bdf, struct pcie_vc_regs *regs);
123 void pcie_vc_load_resources_regs(pcie_bdf_t bdf,
/Zephyr-latest/include/zephyr/drivers/pcie/
Dcontroller.h44 typedef uint32_t (*pcie_ctrl_conf_read_t)(const struct device *dev, pcie_bdf_t bdf,
58 typedef void (*pcie_ctrl_conf_write_t)(const struct device *dev, pcie_bdf_t bdf,
78 typedef bool (*pcie_ctrl_region_allocate_t)(const struct device *dev, pcie_bdf_t bdf,
97 typedef bool (*pcie_ctrl_region_get_allocate_base_t)(const struct device *dev, pcie_bdf_t bdf,
120 typedef bool (*pcie_ctrl_region_translate_t)(const struct device *dev, pcie_bdf_t bdf,
141 uint32_t pcie_generic_ctrl_conf_read(mm_reg_t cfg_addr, pcie_bdf_t bdf, unsigned int reg);
156 void pcie_generic_ctrl_conf_write(mm_reg_t cfg_addr, pcie_bdf_t bdf,
196 static inline uint32_t pcie_ctrl_conf_read(const struct device *dev, pcie_bdf_t bdf, in pcie_ctrl_conf_read() argument
202 return api->conf_read(dev, bdf, reg); in pcie_ctrl_conf_read()
216 static inline void pcie_ctrl_conf_write(const struct device *dev, pcie_bdf_t bdf, in pcie_ctrl_conf_write() argument
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Dmsi.h38 #define PCI_BDF_TO_DEVID(bdf) PCI_DEVID(PCIE_BDF_TO_BUS(bdf), \ argument
39 PCIE_BDF_TO_DEV(bdf), \
40 PCIE_BDF_TO_FUNC(bdf))
52 pcie_bdf_t bdf; member
74 extern uint8_t pcie_msi_vectors_allocate(pcie_bdf_t bdf,
90 extern bool pcie_msi_vector_connect(pcie_bdf_t bdf,
133 extern bool pcie_msi_enable(pcie_bdf_t bdf,
144 extern bool pcie_is_msi(pcie_bdf_t bdf);
Dpcie.h60 pcie_bdf_t bdf; member
98 .bdf = PCIE_BDF_NONE, \
170 extern uint32_t pcie_conf_read(pcie_bdf_t bdf, unsigned int reg);
181 extern void pcie_conf_write(pcie_bdf_t bdf, unsigned int reg, uint32_t data);
191 typedef bool (*pcie_scan_cb_t)(pcie_bdf_t bdf, pcie_id_t id, void *cb_data);
231 extern bool pcie_get_mbar(pcie_bdf_t bdf,
248 extern bool pcie_probe_mbar(pcie_bdf_t bdf,
259 extern bool pcie_get_iobar(pcie_bdf_t bdf,
276 extern bool pcie_probe_iobar(pcie_bdf_t bdf,
287 extern void pcie_set_cmd(pcie_bdf_t bdf, uint32_t bits, bool on);
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Dvc.h62 int pcie_vc_enable(pcie_bdf_t bdf);
69 int pcie_vc_disable(pcie_bdf_t bdf);
84 int pcie_vc_map_tc(pcie_bdf_t bdf, struct pcie_vctc_map *map);
Dptm.h31 bool pcie_ptm_enable(pcie_bdf_t bdf);
/Zephyr-latest/arch/x86/core/
Dpcie.c65 static inline void pcie_mm_conf(pcie_bdf_t bdf, unsigned int reg, in pcie_mm_conf() argument
69 int off = PCIE_BDF_TO_BUS(bdf) - bus_segs[i].start_bus; in pcie_mm_conf()
72 bdf = PCIE_BDF(off, in pcie_mm_conf()
73 PCIE_BDF_TO_DEV(bdf), in pcie_mm_conf()
74 PCIE_BDF_TO_FUNC(bdf)); in pcie_mm_conf()
77 = (void *)&bus_segs[i].mmio[bdf << 4]; in pcie_mm_conf()
104 static inline void pcie_io_conf(pcie_bdf_t bdf, unsigned int reg, in pcie_io_conf() argument
110 bdf &= PCIE_X86_CAP_BDF_MASK; in pcie_io_conf()
111 bdf |= PCIE_X86_CAP_EN; in pcie_io_conf()
112 bdf |= (reg & PCIE_X86_CAP_WORD_MASK) << PCIE_X86_CAP_WORD_SHIFT; in pcie_io_conf()
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/Zephyr-latest/include/zephyr/dt-bindings/pcie/
Dpcie.h70 #define PCIE_BDF_TO_BUS(bdf) (((bdf) >> PCIE_BDF_BUS_SHIFT) & PCIE_BDF_BUS_MASK) argument
71 #define PCIE_BDF_TO_DEV(bdf) (((bdf) >> PCIE_BDF_DEV_SHIFT) & PCIE_BDF_DEV_MASK) argument
73 #define PCIE_BDF_TO_FUNC(bdf) \ argument
74 (((bdf) >> PCIE_BDF_FUNC_SHIFT) & PCIE_BDF_FUNC_MASK)
/Zephyr-latest/tests/subsys/edac/ibecc_cov/src/
Dibecc.c57 static void mock_conf_write(pcie_bdf_t bdf, unsigned int reg, uint32_t data) in mock_conf_write() argument
62 static uint32_t mock_conf_read(pcie_bdf_t bdf, unsigned int reg) in mock_conf_read() argument
65 if (bdf == PCI_HOST_BRIDGE && reg == PCIE_CONF_ID) { in mock_conf_read()
73 if (bdf == PCI_HOST_BRIDGE && reg == CAPID0_C_REG) { in mock_conf_read()
86 #define pcie_conf_read(bdf, reg) mock_conf_read(bdf, reg) argument
87 #define pcie_conf_write(bdf, reg, val) mock_conf_write(bdf, reg, val) argument
/Zephyr-latest/doc/develop/sca/
Dcpptest.rst25 A ``.bdf`` file will be generated as :file:`build/sca/cpptest/cpptestscan.bdf`.
36 …cpptestcli -data out -localsettings local.conf -bdf build/sca/cpptest/cpptestscan.bdf -config "bui…
39 You might need to set ``bdf.import.c.compiler.exec``, ``bdf.import.cpp.compiler.exec``, and
40 ``bdf.import.linker.exec`` to the toolchain :ref:`west build <west-building>` used.
/Zephyr-latest/drivers/virtualization/
Dvirt_ivshmem.c48 n_vectors = pcie_msi_vectors_allocate(data->pcie->bdf, in ivshmem_configure_msi_x_interrupts()
64 if (!pcie_msi_vector_connect(data->pcie->bdf, in ivshmem_configure_msi_x_interrupts()
75 if (!pcie_msi_enable(data->pcie->bdf, data->vectors, n_vectors, 0)) { in ivshmem_configure_msi_x_interrupts()
98 uint32_t cfg_int = pcie_conf_read(data->pcie->bdf, PCIE_CONF_INTR); in ivshmem_configure_int_x_interrupts()
107 pcie_set_cmd(data->pcie->bdf, PCIE_CONF_CMDSTAT_INTX_DISABLE, false); in ivshmem_configure_int_x_interrupts()
117 data->pcie->bdf, intx->irq, intx->priority, in ivshmem_configure_int_x_interrupts()
125 pcie_irq_enable(data->pcie->bdf, intx->irq); in ivshmem_configure_int_x_interrupts()
150 __maybe_unused static uint64_t pcie_conf_read_u64(pcie_bdf_t bdf, unsigned int reg) in pcie_conf_read_u64() argument
152 uint64_t lo = pcie_conf_read(bdf, reg); in pcie_conf_read_u64()
153 uint64_t hi = pcie_conf_read(bdf, reg + 1); in pcie_conf_read_u64()
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/Zephyr-latest/drivers/edac/
Dedac_ibecc.c59 static bool ibecc_enabled(const pcie_bdf_t bdf) in ibecc_enabled() argument
61 return !!(pcie_conf_read(bdf, CAPID0_C_REG) & CAPID0_C_IBECC_ENABLED); in ibecc_enabled()
64 static void ibecc_errcmd_setup(const pcie_bdf_t bdf, bool enable) in ibecc_errcmd_setup() argument
68 errcmd = pcie_conf_read(bdf, ERRCMD_REG); in ibecc_errcmd_setup()
76 pcie_conf_write(bdf, ERRCMD_REG, errcmd); in ibecc_errcmd_setup()
79 static void ibecc_errsts_clear(const pcie_bdf_t bdf) in ibecc_errsts_clear() argument
83 errsts = pcie_conf_read(bdf, ERRSTS_REG); in ibecc_errsts_clear()
89 pcie_conf_write(bdf, ERRSTS_REG, errsts); in ibecc_errsts_clear()
288 const pcie_bdf_t bdf = PCI_HOST_BRIDGE; in edac_ibecc_init() local
293 conf_data = pcie_conf_read(bdf, PCIE_CONF_ID); in edac_ibecc_init()
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/Zephyr-latest/drivers/can/
Dcan_kvaser_pci.c76 if (kvaser_config->pcie->bdf == PCIE_BDF_NONE) { in can_kvaser_pci_init()
81 pcie_set_cmd(kvaser_config->pcie->bdf, PCIE_CONF_CMDSTAT_IO, true); in can_kvaser_pci_init()
84 if (!pcie_probe_iobar(kvaser_config->pcie->bdf, 0, &iobar)) { in can_kvaser_pci_init()
92 if (!pcie_probe_iobar(kvaser_config->pcie->bdf, 1, &iobar)) { in can_kvaser_pci_init()
100 if (!pcie_probe_iobar(kvaser_config->pcie->bdf, 2, &iobar)) { in can_kvaser_pci_init()
/Zephyr-latest/tests/drivers/smbus/smbus_emul/src/
Dsmbus.c29 static uint32_t mock_conf_read(pcie_bdf_t bdf, unsigned int reg) in mock_conf_read() argument
35 static void mock_conf_write(pcie_bdf_t bdf, unsigned int reg, uint32_t data) in mock_conf_write() argument
37 emul_pci_write(bdf, reg, data); in mock_conf_write()
40 #define pcie_conf_write(bdf, reg, val) mock_conf_write(bdf, reg, val) argument
44 #define pcie_conf_read(bdf, reg) mock_conf_read(bdf, reg) argument
Demul.h11 void emul_pci_write(pcie_bdf_t bdf, unsigned int reg, uint32_t value);
/Zephyr-latest/drivers/disk/nvme/
Dnvme_controller.c330 if (nvme_ctrlr_cfg->pcie->bdf == PCIE_BDF_NONE) { in nvme_controller_pcie_configure()
338 PCIE_BDF_TO_BUS(nvme_ctrlr_cfg->pcie->bdf), in nvme_controller_pcie_configure()
339 PCIE_BDF_TO_DEV(nvme_ctrlr_cfg->pcie->bdf), in nvme_controller_pcie_configure()
340 PCIE_BDF_TO_FUNC(nvme_ctrlr_cfg->pcie->bdf)); in nvme_controller_pcie_configure()
342 if (!pcie_get_mbar(nvme_ctrlr_cfg->pcie->bdf, in nvme_controller_pcie_configure()
352 n_vectors = pcie_msi_vectors_allocate(nvme_ctrlr_cfg->pcie->bdf, in nvme_controller_pcie_configure()
363 if (!pcie_msi_enable(nvme_ctrlr_cfg->pcie->bdf, in nvme_controller_pcie_configure()
/Zephyr-latest/drivers/smbus/
Dintel_pch_smbus.c227 if (config->pcie->bdf == PCIE_BDF_NONE) { in pch_smbus_init()
232 val = pcie_conf_read(config->pcie->bdf, PCIE_CONF_CMDSTAT); in pch_smbus_init()
238 pcie_probe_mbar(config->pcie->bdf, 0, &mbar); in pch_smbus_init()
239 pcie_set_cmd(config->pcie->bdf, PCIE_CONF_CMDSTAT_MEM, true); in pch_smbus_init()
247 pcie_set_cmd(config->pcie->bdf, PCIE_CONF_CMDSTAT_IO, true); in pch_smbus_init()
248 val = pcie_conf_read(config->pcie->bdf, PCIE_CONF_BAR4); in pch_smbus_init()
259 val = pcie_conf_read(config->pcie->bdf, PCH_SMBUS_HCFG); in pch_smbus_init()
920 sts = pcie_conf_read(config->pcie->bdf, PCIE_CONF_CMDSTAT); in smbus_isr()
995 irq = pcie_alloc_irq(config->pcie->bdf); \
1001 pcie_conf_write(config->pcie->bdf, \
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/Zephyr-latest/cmake/sca/cpptest/
Dsca.cmake11 set(output_file ${output_dir}/cpptestscan.bdf)

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