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/Zephyr-latest/scripts/tests/twister/
Dtest_quarantine.py69 architectures, argument
79 architectures=architectures,
86 architectures=architectures,
107 architectures=[],
139 architectures=[],
242 architectures=['all'],
248 architectures=['all'],
254 architectures=['unsupported arch 1'],
/Zephyr-latest/scripts/pylib/twister/twisterlib/
Dquarantine.py50 architectures: list[str] = field(default_factory=list) variable in QuarantineElement
65 if 'all' in self.architectures:
66 self.architectures = []
72 self.re_architectures = [re.compile(pat) for pat in self.architectures]
78 if not any([self.scenarios, self.platforms, self.architectures, self.simulations]):
129 qelem.architectures
/Zephyr-latest/tests/arch/arm/arm_custom_interrupt/
DREADME.txt2 the Cortex-M architectures.
7 Cortex-M architectures using the CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER
/Zephyr-latest/doc/services/pm/
Doverview.rst7 architectures.
/Zephyr-latest/doc/services/dsp/
Dindex.rst12 optimized. The status of the various architectures can be found below:
35 architectures to use the zDSP APIs. This can be done by setting::
/Zephyr-latest/tests/kernel/common/
Dmultilib.txt5 Some architectures support different ISA variants, each backed a different
/Zephyr-latest/samples/net/sockets/dumb_http_server/src/
Dresponse_big.html.bin27 …em (RTOS) optimized for resource constrained devices, across multiple architectures. The Zephyr Pr…
31 …less gateways. Because the Zephyr OS is modular and supports multiple architectures, developers ar…
/Zephyr-latest/samples/net/sockets/dumb_http_server_mt/src/
Dresponse_big.html.bin27 …em (RTOS) optimized for resource constrained devices, across multiple architectures. The Zephyr Pr…
31 …less gateways. Because the Zephyr OS is modular and supports multiple architectures, developers ar…
/Zephyr-latest/doc/services/debugging/
Dsymtab.rst10 …, this is being used to look up the function names during a stack trace in supported architectures.
Dmipi_stp_decoder.rst34 * Decoder supports only little endian architectures.
/Zephyr-latest/doc/connectivity/bluetooth/
Dfeatures.rst23 * Portable to all architectures supported by Zephyr (including big and
46 * Supports little and big endian architectures, and abstracts the hard
/Zephyr-latest/doc/_doxygen/
Dmainpage.md15 The Zephyr kernel supports multiple architectures, including ARM
/Zephyr-latest/tests/arch/common/ramfunc/
DREADME.txt1 Title: Test to verify code execution from SRAM for XIP images (only on supported architectures with…
/Zephyr-latest/doc/introduction/
Dindex.rst11 The Zephyr kernel supports multiple architectures, including:
24 The full list of supported boards based on these architectures can be found :ref:`here <boards>`.
99 architectures and developer tools. Contributions have added support
105 with thread-level memory protection on x86, ARC, and ARM architectures,
/Zephyr-latest/doc/develop/toolchains/
Dzephyr_sdk.rst7 Zephyr's supported architectures. It also includes additional host tools, such
11 certain conditions (for example, running tests in QEMU for some architectures).
13 Supported architectures
16 The Zephyr SDK supports the following target architectures:
Dcrosstool_ng.rst20 target architectures.
/Zephyr-latest/samples/subsys/profiling/perf/
DREADME.rst12 The Perf tool is currently implemented only for RISC-V and x86_64 architectures.
/Zephyr-latest/doc/services/
Dnotify.rst9 often a good method, but some application architectures may be more
/Zephyr-latest/boards/
Dindex.rst24 single field, selecting multiple options (such as two architectures) will show boards matching
/Zephyr-latest/
DREADME.rst19 multiple hardware architectures, optimized for resource constrained devices,
26 The Zephyr kernel supports multiple architectures, including ARM (Cortex-A,
/Zephyr-latest/cmake/compiler/arcmwdt/
Dtarget.cmake48 # architectures. __MW_ASM_RV_MACRO__ allows to select appropriate compilation branch.
/Zephyr-latest/samples/modules/cmsis_dsp/moving_average/
DREADME.rst25 processors vs. other architectures, the sample outputs the time and number of cycles it took to
/Zephyr-latest/doc/hardware/cache/
Dguide.rst38 results in a significant performance hit. Many architectures provide methods for
89 use of an MPU region which may be a limited resource on some architectures.
145 Some architectures support a cache configuration called **write-through**
/Zephyr-latest/doc/services/binary_descriptors/
Dindex.rst36 to a known offset in the binary image. This offset may vary between architectures,
38 possible. In architectures where the image must begin with a vector table (such as
40 to the beginning of the text section, which is after the descriptors. In architectures
/Zephyr-latest/boards/renesas/rcar_spider_s4/doc/
Drcar_spider_a55.rst9 high security and high functional safety levels that are required as E/E architectures

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