Home
last modified time | relevance | path

Searched refs:aligned (Results 1 – 25 of 103) sorted by relevance

12345

/Zephyr-latest/boards/arm/fvp_base_revc_2xaemv8a/
DKconfig5 # - LPI prop table: global 1x64K aligned on 64K
6 # - LPI pend table: for each redistributor/cpu 1x64K aligned on 64K
7 # - Devices table: 128x4K aligned on 4K
8 # - Interrupt Collections table: 1x4K aligned on 4K
15 # 256bytes aligned tables, for reference a 32 ITEs table needs 256bytes.
/Zephyr-latest/drivers/flash/
Dflash_ambiq.c90 uint32_t aligned[FLASH_WRITE_BLOCK_SIZE / sizeof(uint32_t)] = {0}; in flash_ambiq_write() local
113 aligned[j] = UNALIGNED_GET((uint32_t *)src); in flash_ambiq_write()
118 AM_HAL_MRAM_PROGRAM_KEY, aligned, in flash_ambiq_write()
123 AM_HAL_FLASH_PROGRAM_KEY, aligned, in flash_ambiq_write()
DKconfig.simulator21 If selected, the reading operation does not check if access is aligned.
23 a specific FLASH interface that requires aligned read access.
/Zephyr-latest/arch/x86/zefi/
Defi.ld20 * need to be page-aligned and can be immediately after text/rodata */
23 /* Must be page-aligned or EFI balks */
/Zephyr-latest/arch/arm/core/
Dvector_table.ld17 * of the vector table is 64-word aligned.
22 * of the vector table is 32-word aligned.
44 * should be aligned in such a way so that it satisfies the requirements of
/Zephyr-latest/drivers/sdhc/
DKconfig.esp3215 # ESP32 DMA needs 32 bit aligned buffers
DKconfig.sdhc_cdns14 # Cadence SDHC DMA needs 64 bit aligned buffers
DKconfig.mcux_sdif24 # SDIF DMA needs 32 bit aligned buffers
DKconfig.imx31 # USDHC DMA needs 32 bit aligned buffers
/Zephyr-latest/soc/aspeed/
Daspeed_util.h20 #define ALIGNED16_SECTION(name) (aligned(16), section(name))
/Zephyr-latest/subsys/bluetooth/controller/util/
Dmem.h13 #define MALIGN(x) __attribute__((aligned(x)))
/Zephyr-latest/boards/shields/rk043fn02h_ct/
DKconfig.defconfig41 # Force display buffers to be aligned to cache line size (32 bytes)
/Zephyr-latest/boards/shields/rk043fn66hs_ctg/
DKconfig.defconfig41 # Force display buffers to be aligned to cache line size (32 bytes)
/Zephyr-latest/drivers/display/
DKconfig.renesas_ra28 # Force display buffers to be aligned to cache line size (64 bytes)
/Zephyr-latest/soc/infineon/cat1b/cyw20829/
Dlinker.ld198 * is 32-bit aligned, but the actual data is placed right after rodata
200 * section, so __data_rom_start points at data and it is 32-bit aligned.
204 * usually 4k aligned.
214 * of the sections in the RAMABLE_REGION are aligned with those
267 * For performance, BSS section is assumed to be 4 byte aligned and
336 * For performance, BSS section is assumed to be 4 byte aligned and
/Zephyr-latest/include/zephyr/arch/arm/cortex_m/scripts/
Dlinker.ld215 * is 32-bit aligned, but the actual data is placed right after rodata
217 * section, so __data_rom_start points at data and it is 32-bit aligned.
221 * usually 4k aligned.
231 * of the sections in the RAMABLE_REGION are aligned with those
284 * For performance, BSS section is assumed to be 4 byte aligned and
456 * For performance, BSS section is assumed to be 4 byte aligned and
/Zephyr-latest/lib/libc/newlib/
DKconfig35 int "Newlib aligned heap size"
41 regions be sized to a power of two and aligned to their size,
/Zephyr-latest/boards/renesas/da1469x_dk_pro/
DKconfig.defconfig16 # LCDC imposes display buffer's stride be word aligned
/Zephyr-latest/arch/arm/core/cortex_m/tz/
Dsecure_entry_functions.ld22 /* The ARM SAU requires regions to be 32-byte-aligned. */
/Zephyr-latest/arch/arm/core/cortex_m/
Drelay_vector_table.ld16 * of the vector table is 32-word aligned.
/Zephyr-latest/doc/kernel/usermode/
Dmpu_stack_objects.rst46 Some MPUs require that each region be aligned to a power of two. These SoCs
48 This means that a 1500 byte stack should be aligned to a 2kB boundary and the
/Zephyr-latest/doc/services/storage/disk/
Dnvme.rst70 NVMe specifications mandate the data buffer to be placed in a dword (4 bytes) aligned address.
76 :c:func:`disk_access_read` and :c:func:`disk_access_write` are dword aligned.
/Zephyr-latest/doc/kernel/memory_management/
Dslabs.rst33 The memory slab's buffer must be aligned to an N-byte boundary, where
35 all memory blocks in the buffer are similarly aligned to this boundary,
74 that are 400 bytes long, each of which is aligned to a 4-byte boundary.
Dsys_mem_blocks.rst43 The buffer must be aligned to an N-byte boundary, where N is a power of 2
45 the buffer are similarly aligned to this boundary, the block size must
108 which has 4 blocks that are 64 bytes long, each of which is aligned
/Zephyr-latest/include/zephyr/arch/arm/cortex_a_r/scripts/
Dlinker.ld222 * is 32-bit aligned, but the actual data is placed right after rodata
224 * section, so __data_rom_start points at data and it is 32-bit aligned.
228 * usually 4k aligned.
288 * For performance, BSS section is assumed to be 4 byte aligned and

12345