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/Zephyr-latest/arch/xtensa/core/
Dcoredump.c80 uint32_t a15; member
176 arch_blk.r.a15 = frame->blks[regs_blk_remaining].r3; in arch_coredump_info_dump()
Dxtensa_asm2_util.S79 s32i a15, a1, 12
126 l32i a15, a2, 12
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dpower_down.S42 #define pfl_reg a15
/Zephyr-latest/soc/intel/intel_adsp/cavs/
Dpower_down_cavs.S44 #define pfl_reg a15
/Zephyr-latest/arch/xtensa/include/
Dxtensa_asm2_context.h187 uintptr_t a15; member