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/Zephyr-latest/arch/riscv/core/
Dpmp.S48 .set _index, 0 define
50 lr t0, (RV_REGSIZE * _index)(a3)
51 li t1, _index + 1
52 csrw (CSR_PMPADDR_BASE + _index), t0
54 .set _index, _index + 1 define
77 .set _index, 0 define
79 lr t0, (RV_REGSIZE * _index)(a4)
81 csrw (CSR_PMPCFG_BASE + RV_REGSIZE/4 * _index), t0
83 .set _index, _index + 1 define
100 .set _index, 0 define
[all …]
/Zephyr-latest/soc/silabs/silabs_sim3/sim3u/
Dgen_crossbar_config.py193 for _index, signal in enumerate(bit.signals):
/Zephyr-latest/doc/
Dzephyr.doxyfile.in1522 # genXcode/_index.html for more information.