| /Zephyr-latest/drivers/memc/ |
| D | memc_smartbond_nor_psram.c | 20 #define CLK_AMBA_REG_SET_FIELD(_field, _var, _val) \ argument
22 ((_var) & ~(CRG_TOP_CLK_AMBA_REG_ ## _field ## _Msk)) | \
23 (((_val) << CRG_TOP_CLK_AMBA_REG_ ## _field ## _Pos) & \
24 CRG_TOP_CLK_AMBA_REG_ ## _field ## _Msk)
26 #define QSPIC2_CTRLMODE_REG_SET_FIELD(_field, _var, _val) \ argument
28 ((_var) & ~(QSPIC2_QSPIC2_CTRLMODE_REG_ ## _field ## _Msk)) | \
29 (((_val) << QSPIC2_QSPIC2_CTRLMODE_REG_ ## _field ## _Pos) & \
30 QSPIC2_QSPIC2_CTRLMODE_REG_ ## _field ## _Msk)
32 #define QSPIC2_BURSTCMDA_REG_SET_FIELD(_field, _var, _val) \ argument
34 ((_var) & ~(QSPIC2_QSPIC2_BURSTCMDA_REG_ ## _field ## _Msk)) | \
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| /Zephyr-latest/drivers/rtc/ |
| D | rtc_smartbond.c | 39 #define RTC_TIME_REG_SET_FIELD(_field, _var, _val) \ argument
41 ((_var) & ~(RTC_RTC_TIME_REG_RTC_TIME_ ## _field ## _T_Msk | \
42 RTC_RTC_TIME_REG_RTC_TIME_ ## _field ## _U_Msk)) | \
43 (((_val) << RTC_RTC_TIME_REG_RTC_TIME_ ## _field ## _U_Pos) & \
44 (RTC_RTC_TIME_REG_RTC_TIME_ ## _field ## _T_Msk | \
45 RTC_RTC_TIME_REG_RTC_TIME_ ## _field ## _U_Msk)))
47 #define RTC_CALENDAR_REG_SET_FIELD(_field, _var, _val) \ argument
49 ((_var) & ~(RTC_RTC_CALENDAR_REG_RTC_CAL_ ## _field ## _T_Msk | \
50 RTC_RTC_CALENDAR_REG_RTC_CAL_ ## _field ## _U_Msk)) | \
51 (((_val) << RTC_RTC_CALENDAR_REG_RTC_CAL_ ## _field ## _U_Pos) & \
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| D | rtc_nxp_irtc.c | 34 #define RTC_NXP_GET_REG_FIELD(_reg, _name, _field) \ argument
35 ((_reg->_name & RTC_##_name##_##_field##_MASK) >> \
36 RTC_##_name##_##_field##_SHIFT)
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| /Zephyr-latest/subsys/net/ip/ |
| D | tp.h | 71 #define json_str(_type, _field) \ argument
72 JSON_OBJ_DESCR_PRIM(struct _type, _field, JSON_TOK_STRING)
73 #define json_num(_type, _field) \ argument
74 JSON_OBJ_DESCR_PRIM(struct _type, _field, JSON_TOK_NUMBER)
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| /Zephyr-latest/drivers/mipi_dbi/ |
| D | mipi_dbi_smartbond.c | 52 #define LCDC_LAYER0_OFFSETX_REG_SET_FIELD(_field, _var, _val) \ argument
54 ((_var) & ~(LCDC_LCDC_LAYER0_OFFSETX_REG_ ## _field ## _Msk)) | \
55 (((_var) << LCDC_LCDC_LAYER0_OFFSETX_REG_ ## _field ## _Pos) & \
56 LCDC_LCDC_LAYER0_OFFSETX_REG_ ## _field ## _Msk)
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| /Zephyr-latest/drivers/dma/ |
| D | dma_smartbond.c | 32 #define DMA_CTRL_REG_SET_FIELD(_field, _var, _val) \ argument
34 (((_var) & ~DMA_DMA0_CTRL_REG_ ## _field ## _Msk) | \
35 (((_val) << DMA_DMA0_CTRL_REG_ ## _field ## _Pos) & DMA_DMA0_CTRL_REG_ ## _field ## _Msk))
37 #define DMA_CTRL_REG_GET_FIELD(_field, _var) \ argument
38 (((_var) & DMA_DMA0_CTRL_REG_ ## _field ## _Msk) >> DMA_DMA0_CTRL_REG_ ## _field ## _Pos)
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| /Zephyr-latest/drivers/crypto/ |
| D | crypto_smartbond.c | 36 #define CRYPTO_CTRL_REG_SET(_field, _val) \ argument
38 (AES_HASH->CRYPTO_CTRL_REG & ~AES_HASH_CRYPTO_CTRL_REG_ ## _field ## _Msk) | \
39 ((_val) << AES_HASH_CRYPTO_CTRL_REG_ ## _field ## _Pos)
41 #define CRYPTO_CTRL_REG_GET(_field) \ argument
42 ((AES_HASH->CRYPTO_CTRL_REG & AES_HASH_CRYPTO_CTRL_REG_ ## _field ## _Msk) >> \
43 AES_HASH_CRYPTO_CTRL_REG_ ## _field ## _Pos)
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| /Zephyr-latest/drivers/display/ |
| D | display_renesas_lcdc.c | 41 #define LCDC_LAYER0_OFFSETX_REG_SET_FIELD(_field, _var, _val)\ argument
43 ((_var) & ~(LCDC_LCDC_LAYER0_OFFSETX_REG_ ## _field ## _Msk)) | \
44 (((_val) << LCDC_LCDC_LAYER0_OFFSETX_REG_ ## _field ## _Pos) & \
45 LCDC_LCDC_LAYER0_OFFSETX_REG_ ## _field ## _Msk)
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| /Zephyr-latest/drivers/spi/ |
| D | spi_smartbond.c | 98 #define SPI_CTRL_REG_SET_FIELD(_field, _var, _val) \ argument
100 (((_var) & ~SPI_SPI_CTRL_REG_ ## _field ## _Msk) | \
101 (((_val) << SPI_SPI_CTRL_REG_ ## _field ## _Pos) & SPI_SPI_CTRL_REG_ ## _field ## _Msk))
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