Searched refs:XTENSA_RSR (Results 1 – 9 of 9) sorted by relevance
23 #define XTENSA_RSR(sr) \ macro67 cpu = (_cpu_t *)XTENSA_RSR(ZSR_CPU_STR); in arch_curr_cpu()
141 core_desc[core_id].ps = XTENSA_RSR("PS"); in _save_core_context()142 core_desc[core_id].vecbase = XTENSA_RSR("VECBASE"); in _save_core_context()143 core_desc[core_id].excsave2 = XTENSA_RSR("EXCSAVE2"); in _save_core_context()144 core_desc[core_id].excsave3 = XTENSA_RSR("EXCSAVE3"); in _save_core_context()147 core_desc[core_id].misc[0] = XTENSA_RSR("MISC0"); in _save_core_context()148 core_desc[core_id].misc[1] = XTENSA_RSR("MISC1"); in _save_core_context()286 core_desc[cpu].intenable = XTENSA_RSR("INTENABLE"); in pm_state_set()
87 core_desc[core_id].ps = XTENSA_RSR("PS"); in _save_core_context()88 core_desc[core_id].excsave2 = XTENSA_RSR(ZSR_CPU_STR); in _save_core_context()141 core_desc[cpu].intenable = XTENSA_RSR("INTENABLE"); in pm_state_set()
25 intenable = XTENSA_RSR("INTENABLE"); in pm_state_set()
23 intenable = XTENSA_RSR("INTENABLE"); in pm_state_set()
30 uint32_t vecbase = XTENSA_RSR("VECBASE"); in compute_regs()
356 depc = XTENSA_RSR(ZSR_DEPC_SAVE_STR); in xtensa_excint1_c()357 cause = XTENSA_RSR(ZSR_EXCCAUSE_SAVE_STR); in xtensa_excint1_c()
290 * Macros ``RSR`` and ``WSR`` have been renamed to :c:macro:`XTENSA_RSR`
