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Searched refs:XTENSA_MMU_PTE_SW_MASK (Results 1 – 1 of 1) sorted by relevance

/Zephyr-latest/arch/xtensa/include/
Dxtensa_mmu_priv.h57 #define XTENSA_MMU_PTE_SW_MASK 0x00000FC0U macro
70 (((sw) << XTENSA_MMU_PTE_SW_SHIFT) & XTENSA_MMU_PTE_SW_MASK) | \
83 (((pte) & ~XTENSA_MMU_PTE_SW_MASK) | (sw << XTENSA_MMU_PTE_SW_SHIFT))
87 (((pte) & XTENSA_MMU_PTE_SW_MASK) >> XTENSA_MMU_PTE_SW_SHIFT)