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Searched refs:XTENSA_IRQ_NUMBER (Results 1 – 12 of 12) sorted by relevance

/Zephyr-latest/soc/intel/intel_adsp/cavs/
Dirq.c30 switch (XTENSA_IRQ_NUMBER(irq)) { in z_soc_irq_enable()
45 xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq)); in z_soc_irq_enable()
58 xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq)); in z_soc_irq_enable()
68 switch (XTENSA_IRQ_NUMBER(irq)) { in z_soc_irq_disable()
83 xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq)); in z_soc_irq_disable()
100 xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq)); in z_soc_irq_disable()
109 switch (XTENSA_IRQ_NUMBER(irq)) { in z_soc_irq_is_enabled()
124 ret = xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq)); in z_soc_irq_is_enabled()
164 switch (XTENSA_IRQ_NUMBER(irq)) { in z_soc_irq_connect_dynamic()
/Zephyr-latest/drivers/interrupt_controller/
Dintc_dw_ace.c96 xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq)); in dw_ace_irq_enable()
112 xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq)); in dw_ace_irq_disable()
123 return xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq)); in dw_ace_irq_is_enabled()
Dintc_nxp_irqsteer.c339 xtensa_irq_enable(XTENSA_IRQ_NUMBER(disp->irq)); in _irqstr_disp_enable_disable()
345 xtensa_irq_disable(XTENSA_IRQ_NUMBER(disp->irq)); in _irqstr_disp_enable_disable()
470 xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq)); in z_soc_irq_enable_disable()
472 xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq)); in z_soc_irq_enable_disable()
517 return xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq)); in z_soc_irq_is_enabled()
/Zephyr-latest/soc/nxp/imx/imx8ulp/adsp/include/
Dsoc.h26 #define XTENSA_IRQ_NUMBER(_irq) \ macro
/Zephyr-latest/soc/nxp/imx/imx8x/adsp/include/
Dsoc.h26 #define XTENSA_IRQ_NUMBER(_irq) \ macro
/Zephyr-latest/soc/nxp/imx/imx8/adsp/include/
Dsoc.h26 #define XTENSA_IRQ_NUMBER(_irq) \ macro
/Zephyr-latest/soc/nxp/imx/imx8m/adsp/include/
Dsoc.h26 #define XTENSA_IRQ_NUMBER(_irq) \ macro
/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/f1/include/
Dsoc.h26 #define XTENSA_IRQ_NUMBER(_irq) \ macro
/Zephyr-latest/soc/intel/intel_adsp/cavs/include/
Dadsp_interrupt.h22 #define XTENSA_IRQ_NUMBER(_irq) \ macro
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace15_mtpm/
Dadsp_interrupt.h80 #define XTENSA_IRQ_NUMBER(_irq) ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK) macro
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace20_lnl/
Dadsp_interrupt.h78 #define XTENSA_IRQ_NUMBER(_irq) ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK) macro
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace30/
Dadsp_interrupt.h78 #define XTENSA_IRQ_NUMBER(_irq) ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK) macro