1 /* 2 * Copyright (c) 2016 Intel Corporation 3 * Copyright (c) 2023 Nordic Semiconductor ASA 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #ifndef ZEPHYR_DRIVERS_USB_COMMON_USB_DWC2_HW 9 #define ZEPHYR_DRIVERS_USB_COMMON_USB_DWC2_HW 10 11 #include <stdint.h> 12 13 #ifdef __cplusplus 14 extern "C" { 15 #endif 16 17 /* This file describes register set for the DesignWare USB 2.0 controller IP */ 18 19 /* IN endpoint register block */ 20 struct usb_dwc2_in_ep { 21 volatile uint32_t diepctl; 22 uint32_t reserved; 23 volatile uint32_t diepint; 24 uint32_t reserved1; 25 volatile uint32_t dieptsiz; 26 volatile uint32_t diepdma; 27 volatile uint32_t dtxfsts; 28 volatile uint32_t diepdmab; 29 }; 30 31 /* OUT endpoint register block */ 32 struct usb_dwc2_out_ep { 33 volatile uint32_t doepctl; 34 uint32_t reserved; 35 volatile uint32_t doepint; 36 uint32_t reserved1; 37 volatile uint32_t doeptsiz; 38 volatile uint32_t doepdma; 39 uint32_t reserved2; 40 volatile uint32_t doepdmab; 41 }; 42 43 /* DWC2 register map 44 * TODO: This should probably be split into global, host, and device register 45 * blocks 46 */ 47 struct usb_dwc2_reg { 48 volatile uint32_t gotgctl; 49 volatile uint32_t gotgint; 50 volatile uint32_t gahbcfg; 51 volatile uint32_t gusbcfg; 52 volatile uint32_t grstctl; 53 volatile uint32_t gintsts; 54 volatile uint32_t gintmsk; 55 volatile uint32_t grxstsr; 56 volatile uint32_t grxstsp; 57 volatile uint32_t grxfsiz; 58 volatile uint32_t gnptxfsiz; 59 volatile uint32_t gnptxsts; 60 volatile uint32_t gi2cctl; 61 volatile uint32_t gpvndctl; 62 volatile uint32_t ggpio; 63 volatile uint32_t guid; 64 volatile uint32_t gsnpsid; 65 volatile uint32_t ghwcfg1; 66 volatile uint32_t ghwcfg2; 67 volatile uint32_t ghwcfg3; 68 volatile uint32_t ghwcfg4; 69 volatile uint32_t glpmcfg; 70 volatile uint32_t gpwrdn; 71 volatile uint32_t gdfifocfg; 72 volatile uint32_t gadpctl; 73 volatile uint32_t grefclk; 74 volatile uint32_t gintmsk2; 75 volatile uint32_t gintsts2; 76 volatile uint32_t reserved1[36]; 77 volatile uint32_t hptxfsiz; 78 union { 79 volatile uint32_t dptxfsiz[15]; 80 volatile uint32_t dieptxf[15]; 81 }; 82 volatile uint32_t reserved2[176]; 83 /* Host mode register 0x0400 .. 0x0670 */ 84 uint32_t reserved3[256]; 85 /* Device mode register 0x0800 .. 0x0D00 */ 86 volatile uint32_t dcfg; 87 volatile uint32_t dctl; 88 volatile uint32_t dsts; 89 uint32_t reserved4; 90 volatile uint32_t diepmsk; 91 volatile uint32_t doepmsk; 92 volatile uint32_t daint; 93 volatile uint32_t daintmsk; 94 volatile uint32_t dtknqr1; 95 volatile uint32_t dtknqr2; 96 volatile uint32_t dvbusdis; 97 volatile uint32_t dvbuspulse; 98 union { 99 volatile uint32_t dtknqr3; 100 volatile uint32_t dthrctl; 101 }; 102 union { 103 volatile uint32_t dtknqr4; 104 volatile uint32_t diepempmsk; 105 }; 106 volatile uint32_t deachint; 107 volatile uint32_t deachintmsk; 108 volatile uint32_t diepeachmsk[16]; 109 volatile uint32_t doepeachmsk[16]; 110 volatile uint32_t reserved5[16]; 111 struct usb_dwc2_in_ep in_ep[16]; 112 struct usb_dwc2_out_ep out_ep[16]; 113 volatile uint32_t reserved6[64]; 114 volatile uint32_t pcgcctl; 115 }; 116 117 /* The last register (PCGCCTL) must be at offset 0xE00. */ 118 BUILD_ASSERT(offsetof(struct usb_dwc2_reg, pcgcctl) == 0x0E00); 119 120 /* 121 * GET_FIELD/SET_FIELD macros below are intended to be used to define functions 122 * to get/set a bitfield of a register from/into a value. They should not be 123 * used to get/set a bitfield consisting of only one bit. 124 */ 125 #define USB_DWC2_GET_FIELD_DEFINE(name, reg_name_and_field) \ 126 static inline uint32_t usb_dwc2_get_##name(const uint32_t value) \ 127 { \ 128 return (value & USB_DWC2_##reg_name_and_field##_MASK) >> \ 129 USB_DWC2_##reg_name_and_field##_POS; \ 130 } 131 132 #define USB_DWC2_SET_FIELD_DEFINE(name, reg_name_and_field) \ 133 static inline uint32_t usb_dwc2_set_##name(const uint32_t value) \ 134 { \ 135 return (value << USB_DWC2_##reg_name_and_field##_POS) & \ 136 USB_DWC2_##reg_name_and_field##_MASK; \ 137 } 138 139 #define USB_DWC2_GET_FIELD_AND_IDX_DEFINE(name, reg_name_and_field) \ 140 static inline uint32_t usb_dwc2_get_##name(const uint32_t value, \ 141 const uint32_t idx) \ 142 { \ 143 return (value & USB_DWC2_##reg_name_and_field##_MASK(idx)) >> \ 144 USB_DWC2_##reg_name_and_field##_POS(idx); \ 145 } 146 147 /* AHB configuration register */ 148 #define USB_DWC2_GAHBCFG 0x0008UL 149 #define USB_DWC2_GAHBCFG_LOA_EOP_WORD_POS 27UL 150 #define USB_DWC2_GAHBCFG_LOA_EOP_WORD_MASK (0x3UL << USB_DWC2_GAHBCFG_LOA_EOP_WORD_POS) 151 #define USB_DWC2_GAHBCFG_LOA_EOP_WORD_ONE 1 152 #define USB_DWC2_GAHBCFG_LOA_EOP_WORD_TWO 2 153 #define USB_DWC2_GAHBCFG_LOA_EOP_BYTE_POS 25UL 154 #define USB_DWC2_GAHBCFG_LOA_EOP_BYTE_MASK (0x3UL << USB_DWC2_GAHBCFG_LOA_EOP_BYTE_POS) 155 #define USB_DWC2_GAHBCFG_LOA_EOP_BYTE_ONE 1 156 #define USB_DWC2_GAHBCFG_LOA_EOP_BYTE_TWO 2 157 #define USB_DWC2_GAHBCFG_INVDESCENDIANESS_POS 24UL 158 #define USB_DWC2_GAHBCFG_INVDESCENDIANESS BIT(USB_DWC2_GAHBCFG_INVDESCENDIANESS_POS) 159 #define USB_DWC2_GAHBCFG_AHBSINGLE_POS 23UL 160 #define USB_DWC2_GAHBCFG_AHBSINGLE BIT(USB_DWC2_GAHBCFG_AHBSINGLE_POS) 161 #define USB_DWC2_GAHBCFG_NOTIALLDMAWRIT_POS 22UL 162 #define USB_DWC2_GAHBCFG_NOTIALLDMAWRIT BIT(USB_DWC2_GAHBCFG_NOTIALLDMAWRIT_POS) 163 #define USB_DWC2_GAHBCFG_REMMEMSUPP_POS 21UL 164 #define USB_DWC2_GAHBCFG_REMMEMSUPP BIT(USB_DWC2_GAHBCFG_REMMEMSUPP_POS) 165 #define USB_DWC2_GAHBCFG_PTXFEMPLVL_POS 8UL 166 #define USB_DWC2_GAHBCFG_PTXFEMPLVL BIT(USB_DWC2_GAHBCFG_PTXFEMPLVL_POS) 167 #define USB_DWC2_GAHBCFG_NPTXFEMPLVL_POS 7UL 168 #define USB_DWC2_GAHBCFG_NPTXFEMPLVL BIT(USB_DWC2_GAHBCFG_NPTXFEMPLVL_POS) 169 #define USB_DWC2_GAHBCFG_DMAEN_POS 5UL 170 #define USB_DWC2_GAHBCFG_DMAEN BIT(USB_DWC2_GAHBCFG_DMAEN_POS) 171 #define USB_DWC2_GAHBCFG_HBSTLEN_POS 1UL 172 #define USB_DWC2_GAHBCFG_HBSTLEN_MASK (0xFUL << USB_DWC2_GAHBCFG_HBSTLEN_POS) 173 #define USB_DWC2_GAHBCFG_HBSTLEN_SINGLE 0 174 #define USB_DWC2_GAHBCFG_HBSTLEN_INCR 1 175 #define USB_DWC2_GAHBCFG_HBSTLEN_INCR4 3 176 #define USB_DWC2_GAHBCFG_HBSTLEN_INCR8 5 177 #define USB_DWC2_GAHBCFG_HBSTLEN_INCR16 7 178 #define USB_DWC2_GAHBCFG_GLBINTRMASK_POS 0UL 179 #define USB_DWC2_GAHBCFG_GLBINTRMASK BIT(USB_DWC2_GAHBCFG_GLBINTRMASK_POS) 180 181 USB_DWC2_SET_FIELD_DEFINE(gahbcfg_loa_eop_word, GAHBCFG_LOA_EOP_WORD) 182 USB_DWC2_SET_FIELD_DEFINE(gahbcfg_loa_eop_byte, GAHBCFG_LOA_EOP_BYTE) 183 USB_DWC2_SET_FIELD_DEFINE(gahbcfg_hbstlen, GAHBCFG_HBSTLEN) 184 USB_DWC2_GET_FIELD_DEFINE(gahbcfg_loa_eop_word, GAHBCFG_LOA_EOP_WORD) 185 USB_DWC2_GET_FIELD_DEFINE(gahbcfg_loa_eop_byte, GAHBCFG_LOA_EOP_BYTE) 186 USB_DWC2_GET_FIELD_DEFINE(gahbcfg_hbstlen, GAHBCFG_HBSTLEN) 187 188 /* USB configuration register */ 189 #define USB_DWC2_GUSBCFG 0x000CUL 190 #define USB_DWC2_GUSBCFG_FORCEDEVMODE_POS 30UL 191 #define USB_DWC2_GUSBCFG_FORCEDEVMODE BIT(USB_DWC2_GUSBCFG_FORCEDEVMODE_POS) 192 #define USB_DWC2_GUSBCFG_FORCEHSTMODE_POS 29UL 193 #define USB_DWC2_GUSBCFG_FORCEHSTMODE BIT(USB_DWC2_GUSBCFG_FORCEHSTMODE_POS) 194 #define USB_DWC2_GUSBCFG_PHYSEL_POS 6UL 195 #define USB_DWC2_GUSBCFG_PHYSEL_USB11 BIT(USB_DWC2_GUSBCFG_PHYSEL_POS) 196 #define USB_DWC2_GUSBCFG_PHYSEL_USB20 0UL 197 #define USB_DWC2_GUSBCFG_ULPI_UTMI_SEL_POS 4UL 198 #define USB_DWC2_GUSBCFG_ULPI_UTMI_SEL_ULPI BIT(USB_DWC2_GUSBCFG_ULPI_UTMI_SEL_POS) 199 #define USB_DWC2_GUSBCFG_ULPI_UTMI_SEL_UTMI 0UL 200 #define USB_DWC2_GUSBCFG_PHYIF_POS 3UL 201 #define USB_DWC2_GUSBCFG_PHYIF_16_BIT BIT(USB_DWC2_GUSBCFG_PHYIF_POS) 202 #define USB_DWC2_GUSBCFG_PHYIF_8_BIT 0UL 203 204 /* Reset register */ 205 #define USB_DWC2_GRSTCTL 0x0010UL 206 #define USB_DWC2_GRSTCTL_AHBIDLE_POS 31UL 207 #define USB_DWC2_GRSTCTL_AHBIDLE BIT(USB_DWC2_GRSTCTL_AHBIDLE_POS) 208 #define USB_DWC2_GRSTCTL_CSFTRSTDONE_POS 29UL 209 #define USB_DWC2_GRSTCTL_CSFTRSTDONE BIT(USB_DWC2_GRSTCTL_CSFTRSTDONE_POS) 210 #define USB_DWC2_GRSTCTL_TXFNUM_POS 6UL 211 #define USB_DWC2_GRSTCTL_TXFNUM_MASK (0x1FUL << USB_DWC2_GRSTCTL_TXFNUM_POS) 212 #define USB_DWC2_GRSTCTL_TXFFLSH_POS 5UL 213 #define USB_DWC2_GRSTCTL_TXFFLSH BIT(USB_DWC2_GRSTCTL_TXFFLSH_POS) 214 #define USB_DWC2_GRSTCTL_RXFFLSH_POS 4UL 215 #define USB_DWC2_GRSTCTL_RXFFLSH BIT(USB_DWC2_GRSTCTL_RXFFLSH_POS) 216 #define USB_DWC2_GRSTCTL_CSFTRST_POS 0UL 217 #define USB_DWC2_GRSTCTL_CSFTRST BIT(USB_DWC2_GRSTCTL_CSFTRST_POS) 218 219 USB_DWC2_SET_FIELD_DEFINE(grstctl_txfnum, GRSTCTL_TXFNUM) 220 221 /* Core interrupt registers */ 222 #define USB_DWC2_GINTSTS 0x0014UL 223 #define USB_DWC2_GINTMSK 0x0018UL 224 #define USB_DWC2_GINTSTS_WKUPINT_POS 31UL 225 #define USB_DWC2_GINTSTS_WKUPINT BIT(USB_DWC2_GINTSTS_WKUPINT_POS) 226 #define USB_DWC2_GINTSTS_SESSREQINT_POS 30UL 227 #define USB_DWC2_GINTSTS_SESSREQINT BIT(USB_DWC2_GINTSTS_SESSREQINT_POS) 228 #define USB_DWC2_GINTSTS_DISCONNINT_POS 29UL 229 #define USB_DWC2_GINTSTS_DISCONNINT BIT(USB_DWC2_GINTSTS_DISCONNINT_POS) 230 #define USB_DWC2_GINTSTS_CONIDSTSCHNG_POS 28UL 231 #define USB_DWC2_GINTSTS_CONIDSTSCHNG BIT(USB_DWC2_GINTSTS_CONIDSTSCHNG_POS) 232 #define USB_DWC2_GINTSTS_LPM_INT_POS 27UL 233 #define USB_DWC2_GINTSTS_LPM_INT BIT(USB_DWC2_GINTSTS_LPM_INT_POS) 234 #define USB_DWC2_GINTSTS_HCHINT_POS 25UL 235 #define USB_DWC2_GINTSTS_HCHINT BIT(USB_DWC2_GINTSTS_HCHINT_POS) 236 #define USB_DWC2_GINTSTS_PRTINT_POS 24UL 237 #define USB_DWC2_GINTSTS_PRTINT BIT(USB_DWC2_GINTSTS_PRTINT_POS) 238 #define USB_DWC2_GINTSTS_RESETDET_POS 23UL 239 #define USB_DWC2_GINTSTS_RESETDET BIT(USB_DWC2_GINTSTS_RESETDET_POS) 240 #define USB_DWC2_GINTSTS_FETSUSP_POS 22UL 241 #define USB_DWC2_GINTSTS_FETSUSP BIT(USB_DWC2_GINTSTS_FETSUSP_POS) 242 #define USB_DWC2_GINTSTS_INCOMPIP_POS 21UL 243 #define USB_DWC2_GINTSTS_INCOMPIP BIT(USB_DWC2_GINTSTS_INCOMPIP_POS) 244 #define USB_DWC2_GINTSTS_INCOMPISOOUT USB_DWC2_GINTSTS_INCOMPIP 245 #define USB_DWC2_GINTSTS_INCOMPISOIN_POS 20UL 246 #define USB_DWC2_GINTSTS_INCOMPISOIN BIT(USB_DWC2_GINTSTS_INCOMPISOIN_POS) 247 #define USB_DWC2_GINTSTS_OEPINT_POS 19UL 248 #define USB_DWC2_GINTSTS_OEPINT BIT(USB_DWC2_GINTSTS_OEPINT_POS) 249 #define USB_DWC2_GINTSTS_IEPINT_POS 18UL 250 #define USB_DWC2_GINTSTS_IEPINT BIT(USB_DWC2_GINTSTS_IEPINT_POS) 251 #define USB_DWC2_GINTSTS_EPMIS_POS 17UL 252 #define USB_DWC2_GINTSTS_EPMIS BIT(USB_DWC2_GINTSTS_EPMIS_POS) 253 #define USB_DWC2_GINTSTS_RSTRDONEINT_POS 16UL 254 #define USB_DWC2_GINTSTS_RSTRDONEINT BIT(USB_DWC2_GINTSTS_RSTRDONEINT_POS) 255 #define USB_DWC2_GINTSTS_EOPF_POS 15UL 256 #define USB_DWC2_GINTSTS_EOPF BIT(USB_DWC2_GINTSTS_EOPF_POS) 257 #define USB_DWC2_GINTSTS_ISOOUTDROP_POS 14UL 258 #define USB_DWC2_GINTSTS_ISOOUTDROP BIT(USB_DWC2_GINTSTS_ISOOUTDROP_POS) 259 #define USB_DWC2_GINTSTS_ENUMDONE_POS 13UL 260 #define USB_DWC2_GINTSTS_ENUMDONE BIT(USB_DWC2_GINTSTS_ENUMDONE_POS) 261 #define USB_DWC2_GINTSTS_USBRST_POS 12UL 262 #define USB_DWC2_GINTSTS_USBRST BIT(USB_DWC2_GINTSTS_USBRST_POS) 263 #define USB_DWC2_GINTSTS_USBSUSP_POS 11UL 264 #define USB_DWC2_GINTSTS_USBSUSP BIT(USB_DWC2_GINTSTS_USBSUSP_POS) 265 #define USB_DWC2_GINTSTS_ERLYSUSP_POS 10UL 266 #define USB_DWC2_GINTSTS_ERLYSUSP BIT(USB_DWC2_GINTSTS_ERLYSUSP_POS) 267 #define USB_DWC2_GINTSTS_GOUTNAKEFF_POS 7UL 268 #define USB_DWC2_GINTSTS_GOUTNAKEFF BIT(USB_DWC2_GINTSTS_GOUTNAKEFF_POS) 269 #define USB_DWC2_GINTSTS_GINNAKEFF_POS 6UL 270 #define USB_DWC2_GINTSTS_GINNAKEFF BIT(USB_DWC2_GINTSTS_GINNAKEFF_POS) 271 #define USB_DWC2_GINTSTS_NPTXFEMP_POS 5UL 272 #define USB_DWC2_GINTSTS_NPTXFEMP BIT(USB_DWC2_GINTSTS_NPTXFEMP_POS) 273 #define USB_DWC2_GINTSTS_RXFLVL_POS 4UL 274 #define USB_DWC2_GINTSTS_RXFLVL BIT(USB_DWC2_GINTSTS_RXFLVL_POS) 275 #define USB_DWC2_GINTSTS_SOF_POS 3UL 276 #define USB_DWC2_GINTSTS_SOF BIT(USB_DWC2_GINTSTS_SOF_POS) 277 #define USB_DWC2_GINTSTS_OTGINT_POS 2UL 278 #define USB_DWC2_GINTSTS_OTGINT BIT(USB_DWC2_GINTSTS_OTGINT_POS) 279 #define USB_DWC2_GINTSTS_MODEMIS_POS 1UL 280 #define USB_DWC2_GINTSTS_MODEMIS BIT(USB_DWC2_GINTSTS_MODEMIS_POS) 281 #define USB_DWC2_GINTSTS_CURMOD_POS 0UL 282 #define USB_DWC2_GINTSTS_CURMOD BIT(USB_DWC2_GINTSTS_CURMOD_POS) 283 284 /* Status read and pop registers */ 285 #define USB_DWC2_GRXSTSR 0x001CUL 286 #define USB_DWC2_GRXSTSP 0x0020UL 287 #define USB_DWC2_GRXSTSR_FN_POS 21UL 288 #define USB_DWC2_GRXSTSR_FN_MASK (0xFUL << USB_DWC2_GRXSTSR_FN_POS) 289 #define USB_DWC2_GRXSTSR_PKTSTS_POS 17UL 290 #define USB_DWC2_GRXSTSR_PKTSTS_MASK (0xFUL << USB_DWC2_GRXSTSR_PKTSTS_POS) 291 #define USB_DWC2_GRXSTSR_PKTSTS_GLOBAL_OUT_NAK 1 292 #define USB_DWC2_GRXSTSR_PKTSTS_OUT_DATA 2 293 #define USB_DWC2_GRXSTSR_PKTSTS_OUT_DATA_DONE 3 294 #define USB_DWC2_GRXSTSR_PKTSTS_SETUP_DONE 4 295 #define USB_DWC2_GRXSTSR_PKTSTS_SETUP 6 296 #define USB_DWC2_GRXSTSR_DPID_POS 15UL 297 #define USB_DWC2_GRXSTSR_DPID_MASK (0x3UL << USB_DWC2_GRXSTSR_DPID_POS) 298 #define USB_DWC2_GRXSTSR_DPID_DATA0 0 299 #define USB_DWC2_GRXSTSR_DPID_DATA2 1 300 #define USB_DWC2_GRXSTSR_DPID_DATA1 2 301 #define USB_DWC2_GRXSTSR_DPID_MDATA 3 302 #define USB_DWC2_GRXSTSR_BCNT_POS 4UL 303 #define USB_DWC2_GRXSTSR_BCNT_MASK (0x000007FFUL << USB_DWC2_GRXSTSR_BCNT_POS) 304 #define USB_DWC2_GRXSTSR_EPNUM_POS 0UL 305 #define USB_DWC2_GRXSTSR_EPNUM_MASK 0x0000000FUL 306 #define USB_DWC2_GRXSTSR_CHNUM_POS 0UL 307 #define USB_DWC2_GRXSTSR_CHNUM_MASK 0x0000000FUL 308 309 USB_DWC2_GET_FIELD_DEFINE(grxstsp_fn, GRXSTSR_FN) 310 USB_DWC2_GET_FIELD_DEFINE(grxstsp_pktsts, GRXSTSR_PKTSTS) 311 USB_DWC2_GET_FIELD_DEFINE(grxstsp_bcnt, GRXSTSR_BCNT) 312 USB_DWC2_GET_FIELD_DEFINE(grxstsp_epnum, GRXSTSR_EPNUM) 313 314 /* Receive FIFO size register (device mode) */ 315 #define USB_DWC2_GRXFSIZ 0x0024UL 316 #define USB_DWC2_GRXFSIZ_RXFDEP_POS 0UL 317 #define USB_DWC2_GRXFSIZ_RXFDEP_MASK (0xFFFFUL << USB_DWC2_GRXFSIZ_RXFDEP_POS) 318 319 USB_DWC2_GET_FIELD_DEFINE(grxfsiz, GRXFSIZ_RXFDEP) 320 USB_DWC2_SET_FIELD_DEFINE(grxfsiz, GRXFSIZ_RXFDEP) 321 322 /* Non-periodic transmit FIFO size register (device mode) */ 323 #define USB_DWC2_GNPTXFSIZ 0x0028UL 324 #define USB_DWC2_GNPTXFSIZ_NPTXFDEP_POS 16UL 325 #define USB_DWC2_GNPTXFSIZ_NPTXFDEP_MASK (0xFFFFUL << USB_DWC2_GNPTXFSIZ_NPTXFDEP_POS) 326 #define USB_DWC2_GNPTXFSIZ_NPTXFSTADDR_POS 0UL 327 #define USB_DWC2_GNPTXFSIZ_NPTXFSTADDR_MASK (0xFFFFUL << USB_DWC2_GNPTXFSIZ_NPTXFSTADDR_POS) 328 329 USB_DWC2_GET_FIELD_DEFINE(gnptxfsiz_nptxfdep, GNPTXFSIZ_NPTXFDEP) 330 USB_DWC2_GET_FIELD_DEFINE(gnptxfsiz_nptxfstaddr, GNPTXFSIZ_NPTXFSTADDR) 331 USB_DWC2_SET_FIELD_DEFINE(gnptxfsiz_nptxfdep, GNPTXFSIZ_NPTXFDEP) 332 USB_DWC2_SET_FIELD_DEFINE(gnptxfsiz_nptxfstaddr, GNPTXFSIZ_NPTXFSTADDR) 333 334 /* Application (vendor) general purpose registers */ 335 #define USB_DWC2_GGPIO 0x0038UL 336 #define USB_DWC2_GGPIO_STM32_VBDEN_POS 21UL 337 #define USB_DWC2_GGPIO_STM32_VBDEN BIT(USB_DWC2_GGPIO_STM32_VBDEN_POS) 338 #define USB_DWC2_GGPIO_STM32_PWRDWN_POS 16UL 339 #define USB_DWC2_GGPIO_STM32_PWRDWN BIT(USB_DWC2_GGPIO_STM32_PWRDWN_POS) 340 341 /* GSNPSID register */ 342 #define USB_DWC2_GSNPSID_REV_5_00A 0x4F54500AUL 343 344 /* GHWCFG1 register */ 345 #define USB_DWC2_GHWCFG1 0x0044UL 346 #define USB_DWC2_GHWCFG1_EPDIR_POS(i) (i * 2) 347 #define USB_DWC2_GHWCFG1_EPDIR_MASK(i) (0x3UL << USB_DWC2_GHWCFG1_EPDIR_POS(i)) 348 #define USB_DWC2_GHWCFG1_EPDIR_OUT 2 349 #define USB_DWC2_GHWCFG1_EPDIR_IN 1 350 #define USB_DWC2_GHWCFG1_EPDIR_BDIR 0 351 352 USB_DWC2_GET_FIELD_AND_IDX_DEFINE(ghwcfg1_epdir, GHWCFG1_EPDIR) 353 354 /* GHWCFG2 register */ 355 #define USB_DWC2_GHWCFG2 0x0048UL 356 #define USB_DWC2_GHWCFG2_TKNQDEPTH_POS 26UL 357 #define USB_DWC2_GHWCFG2_TKNQDEPTH_MASK (0x1FUL << USB_DWC2_GHWCFG2_TKNQDEPTH_POS) 358 #define USB_DWC2_GHWCFG2_PTXQDEPTH_POS 24UL 359 #define USB_DWC2_GHWCFG2_PTXQDEPTH_MASK (0x3UL << USB_DWC2_GHWCFG2_PTXQDEPTH_POS) 360 #define USB_DWC2_GHWCFG2_PTXQDEPTH_QUE16 3 361 #define USB_DWC2_GHWCFG2_PTXQDEPTH_QUE8 2 362 #define USB_DWC2_GHWCFG2_PTXQDEPTH_QUE4 1 363 #define USB_DWC2_GHWCFG2_PTXQDEPTH_QUE2 0 364 #define USB_DWC2_GHWCFG2_NPTXQDEPTH_POS 22UL 365 #define USB_DWC2_GHWCFG2_NPTXQDEPTH_MASK (0x3UL << USB_DWC2_GHWCFG2_NPTXQDEPTH_POS) 366 #define USB_DWC2_GHWCFG2_NPTXQDEPTH_EIGHT 2 367 #define USB_DWC2_GHWCFG2_NPTXQDEPTH_FOUR 1 368 #define USB_DWC2_GHWCFG2_NPTXQDEPTH_TWO 0 369 #define USB_DWC2_GHWCFG2_MULTIPROCINTRPT_POS 20UL 370 #define USB_DWC2_GHWCFG2_MULTIPROCINTRPT BIT(USB_DWC2_GHWCFG2_MULTIPROCINTRPT_POS) 371 #define USB_DWC2_GHWCFG2_DYNFIFOSIZING_POS 19UL 372 #define USB_DWC2_GHWCFG2_DYNFIFOSIZING BIT(USB_DWC2_GHWCFG2_DYNFIFOSIZING_POS) 373 #define USB_DWC2_GHWCFG2_PERIOSUPPORT_POS 18UL 374 #define USB_DWC2_GHWCFG2_PERIOSUPPORT BIT(USB_DWC2_GHWCFG2_PERIOSUPPORT_POS) 375 #define USB_DWC2_GHWCFG2_NUMHSTCHNL_POS 14UL 376 #define USB_DWC2_GHWCFG2_NUMHSTCHNL_MASK (0xFUL << USB_DWC2_GHWCFG2_NUMHSTCHNL_POS) 377 #define USB_DWC2_GHWCFG2_NUMDEVEPS_POS 10UL 378 #define USB_DWC2_GHWCFG2_NUMDEVEPS_MASK (0xFUL << USB_DWC2_GHWCFG2_NUMDEVEPS_POS) 379 #define USB_DWC2_GHWCFG2_FSPHYTYPE_POS 8UL 380 #define USB_DWC2_GHWCFG2_FSPHYTYPE_MASK (0x3UL << USB_DWC2_GHWCFG2_FSPHYTYPE_POS) 381 #define USB_DWC2_GHWCFG2_FSPHYTYPE_FSPLUSULPI 3 382 #define USB_DWC2_GHWCFG2_FSPHYTYPE_FSPLUSUTMI 2 383 #define USB_DWC2_GHWCFG2_FSPHYTYPE_FS 1 384 #define USB_DWC2_GHWCFG2_FSPHYTYPE_NO_FS 0 385 #define USB_DWC2_GHWCFG2_HSPHYTYPE_POS 6UL 386 #define USB_DWC2_GHWCFG2_HSPHYTYPE_MASK (0x3UL << USB_DWC2_GHWCFG2_HSPHYTYPE_POS) 387 #define USB_DWC2_GHWCFG2_HSPHYTYPE_UTMIPLUSULPI 3 388 #define USB_DWC2_GHWCFG2_HSPHYTYPE_ULPI 2 389 #define USB_DWC2_GHWCFG2_HSPHYTYPE_UTMIPLUS 1 390 #define USB_DWC2_GHWCFG2_HSPHYTYPE_NO_HS 0 391 #define USB_DWC2_GHWCFG2_SINGPNT_POS 5UL 392 #define USB_DWC2_GHWCFG2_SINGPNT BIT(USB_DWC2_GHWCFG2_SINGPNT_POS) 393 #define USB_DWC2_GHWCFG2_OTGARCH_POS 3UL 394 #define USB_DWC2_GHWCFG2_OTGARCH_MASK (0x3UL << USB_DWC2_GHWCFG2_OTGARCH_POS) 395 #define USB_DWC2_GHWCFG2_OTGARCH_INTERNALDMA 2 396 #define USB_DWC2_GHWCFG2_OTGARCH_EXTERNALDMA 1 397 #define USB_DWC2_GHWCFG2_OTGARCH_SLAVEMODE 0 398 #define USB_DWC2_GHWCFG2_OTGMODE_POS 0UL 399 #define USB_DWC2_GHWCFG2_OTGMODE_MASK (0x7UL << USB_DWC2_GHWCFG2_OTGMODE_POS) 400 #define USB_DWC2_GHWCFG2_OTGMODE_NONOTGH 6 401 #define USB_DWC2_GHWCFG2_OTGMODE_SRPCAPH 5 402 #define USB_DWC2_GHWCFG2_OTGMODE_NONOTGD 4 403 #define USB_DWC2_GHWCFG2_OTGMODE_SRPCAPD 3 404 #define USB_DWC2_GHWCFG2_OTGMODE_NHNPNSRP 2 405 #define USB_DWC2_GHWCFG2_OTGMODE_SRPOTG 1 406 #define USB_DWC2_GHWCFG2_OTGMODE_HNPSRP 0 407 408 USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_tknqdepth, GHWCFG2_TKNQDEPTH) 409 USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_ptxqdepth, GHWCFG2_PTXQDEPTH) 410 USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_nptxqdepth, GHWCFG2_NPTXQDEPTH) 411 USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_numhstchnl, GHWCFG2_NUMHSTCHNL) 412 USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_numdeveps, GHWCFG2_NUMDEVEPS) 413 USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_fsphytype, GHWCFG2_FSPHYTYPE) 414 USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_hsphytype, GHWCFG2_HSPHYTYPE) 415 USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_otgarch, GHWCFG2_OTGARCH) 416 USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_otgmode, GHWCFG2_OTGMODE) 417 418 /* GHWCFG3 register */ 419 #define USB_DWC2_GHWCFG3 0x004CUL 420 #define USB_DWC2_GHWCFG3_DFIFODEPTH_POS 16UL 421 #define USB_DWC2_GHWCFG3_DFIFODEPTH_MASK (0xFFFFUL << USB_DWC2_GHWCFG3_DFIFODEPTH_POS) 422 #define USB_DWC2_GHWCFG3_LPMMODE_POS 15UL 423 #define USB_DWC2_GHWCFG3_LPMMODE BIT(USB_DWC2_GHWCFG3_LPMMODE_POS) 424 #define USB_DWC2_GHWCFG3_BCSUPPORT_POS 14UL 425 #define USB_DWC2_GHWCFG3_BCSUPPORT BIT(USB_DWC2_GHWCFG3_BCSUPPORT_POS) 426 #define USB_DWC2_GHWCFG3_HSICMODE_POS 13UL 427 #define USB_DWC2_GHWCFG3_HSICMODE BIT(USB_DWC2_GHWCFG3_HSICMODE_POS) 428 #define USB_DWC2_GHWCFG3_ADPSUPPORT_POS 12UL 429 #define USB_DWC2_GHWCFG3_ADPSUPPORT BIT(USB_DWC2_GHWCFG3_ADPSUPPORT_POS) 430 #define USB_DWC2_GHWCFG3_RSTTYPE_POS 11UL 431 #define USB_DWC2_GHWCFG3_RSTTYPE BIT(USB_DWC2_GHWCFG3_RSTTYPE_POS) 432 #define USB_DWC2_GHWCFG3_OPTFEATURE_POS 10UL 433 #define USB_DWC2_GHWCFG3_OPTFEATURE BIT(USB_DWC2_GHWCFG3_OPTFEATURE_POS) 434 #define USB_DWC2_GHWCFG3_VNDCTLSUPT_POS 9UL 435 #define USB_DWC2_GHWCFG3_VNDCTLSUPT BIT(USB_DWC2_GHWCFG3_VNDCTLSUPT_POS) 436 #define USB_DWC2_GHWCFG3_I2CINTSEL_POS 8UL 437 #define USB_DWC2_GHWCFG3_I2CINTSEL BIT(USB_DWC2_GHWCFG3_I2CINTSEL) 438 #define USB_DWC2_GHWCFG3_OTGEN_POS 7UL 439 #define USB_DWC2_GHWCFG3_OTGEN BIT(USB_DWC2_GHWCFG3_OTGEN_POS) 440 #define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_POS 4UL 441 #define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_MASK (0x7UL << USB_DWC2_GHWCFG3_PKTSIZEWIDTH_POS) 442 #define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_BITS10 6U 443 #define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_BITS9 5U 444 #define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_BITS8 4U 445 #define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_BITS7 3U 446 #define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_BITS6 2U 447 #define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_BITS5 1U 448 #define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_BITS4 0U 449 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_POS 0UL 450 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_MASK (0xFUL << USB_DWC2_GHWCFG3_XFERSIZEWIDTH_POS) 451 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_WIDTH19 8U 452 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_WIDTH18 7U 453 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_WIDTH17 6U 454 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_WIDTH16 5U 455 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_WIDTH15 4U 456 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_WIDTH14 3U 457 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_WIDTH13 2U 458 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_WIDTH12 1U 459 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_WIDTH11 0U 460 461 #define GHWCFG3_PKTCOUNT(pktsizewidth) BIT_MASK(pktsizewidth + 4) 462 #define GHWCFG3_XFERSIZE(xfersizewidth) BIT_MASK(xfersizewidth + 11) 463 464 USB_DWC2_GET_FIELD_DEFINE(ghwcfg3_dfifodepth, GHWCFG3_DFIFODEPTH) 465 USB_DWC2_GET_FIELD_DEFINE(ghwcfg3_pktsizewidth, GHWCFG3_PKTSIZEWIDTH) 466 USB_DWC2_GET_FIELD_DEFINE(ghwcfg3_xfersizewidth, GHWCFG3_XFERSIZEWIDTH) 467 468 /* GHWCFG4 register */ 469 #define USB_DWC2_GHWCFG4 0x0050UL 470 #define USB_DWC2_GHWCFG4_DESCDMA_POS 31UL 471 #define USB_DWC2_GHWCFG4_DESCDMA BIT(USB_DWC2_GHWCFG4_DESCDMA_POS) 472 #define USB_DWC2_GHWCFG4_DESCDMAENABLED_POS 30UL 473 #define USB_DWC2_GHWCFG4_DESCDMAENABLED BIT(USB_DWC2_GHWCFG4_DESCDMAENABLED_POS) 474 #define USB_DWC2_GHWCFG4_INEPS_POS 26UL 475 #define USB_DWC2_GHWCFG4_INEPS_MASK (0xFUL << USB_DWC2_GHWCFG4_INEPS_POS) 476 #define USB_DWC2_GHWCFG4_DEDFIFOMODE_POS 25UL 477 #define USB_DWC2_GHWCFG4_DEDFIFOMODE BIT(USB_DWC2_GHWCFG4_DEDFIFOMODE_POS) 478 #define USB_DWC2_GHWCFG4_SESSENDFLTR_POS 24UL 479 #define USB_DWC2_GHWCFG4_SESSENDFLTR BIT(USB_DWC2_GHWCFG4_SESSENDFLTR_POS) 480 #define USB_DWC2_GHWCFG4_BVALIDFLTR_POS 23UL 481 #define USB_DWC2_GHWCFG4_BVALIDFLTR BIT(USB_DWC2_GHWCFG4_BVALIDFLTR_POS) 482 #define USB_DWC2_GHWCFG4_AVALIDFLTR_POS 22UL 483 #define USB_DWC2_GHWCFG4_AVALIDFLTR BIT(USB_DWC2_GHWCFG4_AVALIDFLTR_POS) 484 #define USB_DWC2_GHWCFG4_VBUSVALIDFLTR_POS 21UL 485 #define USB_DWC2_GHWCFG4_VBUSVALIDFLTR BIT(USB_DWC2_GHWCFG4_VBUSVALIDFLTR_POS) 486 #define USB_DWC2_GHWCFG4_IDDGFLTR_POS 20UL 487 #define USB_DWC2_GHWCFG4_IDDGFLTR BIT(USB_DWC2_GHWCFG4_IDDGFLTR_POS) 488 #define USB_DWC2_GHWCFG4_NUMCTLEPS_POS 16UL 489 #define USB_DWC2_GHWCFG4_NUMCTLEPS_MASK (0xFUL << USB_DWC2_GHWCFG4_NUMCTLEPS_POS) 490 #define USB_DWC2_GHWCFG4_PHYDATAWIDTH_POS 14UL 491 #define USB_DWC2_GHWCFG4_PHYDATAWIDTH_MASK (0x3UL << USB_DWC2_GHWCFG4_PHYDATAWIDTH_POS) 492 #define USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT_POS 13UL 493 #define USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT BIT(USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT_POS) 494 #define USB_DWC2_GHWCFG4_ACGSUPT_POS 12UL 495 #define USB_DWC2_GHWCFG4_ACGSUPT BIT(USB_DWC2_GHWCFG4_ACGSUPT_POS) 496 #define USB_DWC2_GHWCFG4_IPGISOCSUPT_POS 11UL 497 #define USB_DWC2_GHWCFG4_IPGISOCSUPT BIT(USB_DWC2_GHWCFG4_IPGISOCSUPT_POS) 498 #define USB_DWC2_GHWCFG4_SERVINTFLOW_POS 10UL 499 #define USB_DWC2_GHWCFG4_SERVINTFLOW BIT(USB_DWC2_GHWCFG4_SERVINTFLOW_POS) 500 #define USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT1_POS 9UL 501 #define USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT1 BIT(USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT1_POS) 502 #define USB_DWC2_GHWCFG4_EXT_HIBERNATION_POS 7UL 503 #define USB_DWC2_GHWCFG4_EXT_HIBERNATION BIT(USB_DWC2_GHWCFG4_EXT_HIBERNATION_POS) 504 #define USB_DWC2_GHWCFG4_HIBERNATION_POS 6UL 505 #define USB_DWC2_GHWCFG4_HIBERNATION BIT(USB_DWC2_GHWCFG4_HIBERNATION_POS) 506 #define USB_DWC2_GHWCFG4_AHBFREQ_POS 5UL 507 #define USB_DWC2_GHWCFG4_AHBFREQ BIT(USB_DWC2_GHWCFG4_AHBFREQ_POS) 508 #define USB_DWC2_GHWCFG4_PARTIALPWRDN_POS 4UL 509 #define USB_DWC2_GHWCFG4_PARTIALPWRDN BIT(USB_DWC2_GHWCFG4_PARTIALPWRDN_POS) 510 #define USB_DWC2_GHWCFG4_NUMDEVPERIOEPS_POS 0UL 511 #define USB_DWC2_GHWCFG4_NUMDEVPERIOEPS_MASK (0xFUL << USB_DWC2_GHWCFG4_NUMDEVPERIOEPS_POS) 512 513 USB_DWC2_GET_FIELD_DEFINE(ghwcfg4_ineps, GHWCFG4_INEPS) 514 USB_DWC2_GET_FIELD_DEFINE(ghwcfg4_numctleps, GHWCFG4_NUMCTLEPS) 515 USB_DWC2_GET_FIELD_DEFINE(ghwcfg4_phydatawidth, GHWCFG4_PHYDATAWIDTH) 516 USB_DWC2_GET_FIELD_DEFINE(ghwcfg4_numdevperioeps, GHWCFG4_NUMDEVPERIOEPS) 517 518 /* LPM Config Register */ 519 #define USB_DWC2_GLPMCFG 0x0054UL 520 #define USB_DWC2_GLPMCFG_LPM_RESTORESLPSTS_POS 29UL 521 #define USB_DWC2_GLPMCFG_LPM_RESTORESLPSTS BIT(USB_DWC2_GLPMCFG_LPM_RESTORESLPSTS_POS) 522 #define USB_DWC2_GLPMCFG_LPM_ENBESL_POS 28UL 523 #define USB_DWC2_GLPMCFG_LPM_ENBESL BIT(USB_DWC2_GLPMCFG_LPM_ENBESL_POS) 524 #define USB_DWC2_GLPMCFG_LPM_RETRYCNT_STS_POS 25UL 525 #define USB_DWC2_GLPMCFG_LPM_RETRYCNT_STS_MASK (0x7UL << USB_DWC2_GLPMCFG_LPM_RETRYCNT_STS_POS) 526 #define USB_DWC2_GLPMCFG_SNDLPM_POS 24UL 527 #define USB_DWC2_GLPMCFG_SNDLPM BIT(USB_DWC2_GLPMCFG_SNDLPM_POS) 528 /* Host mode LPM Retry Count and LPM Channel Index */ 529 #define USB_DWC2_GLPMCFG_LPM_RETRY_CNT_POS 21UL 530 #define USB_DWC2_GLPMCFG_LPM_RETRY_CNT_MASK (0x7UL << USB_DWC2_GLPMCFG_LPM_RETRY_CNT_POS) 531 #define USB_DWC2_GLPMCFG_LPM_CHNL_INDX_POS 17UL 532 #define USB_DWC2_GLPMCFG_LPM_CHNL_INDX_MASK (0xFUL << USB_DWC2_GLPMCFG_LPM_CHNL_INDX_POS) 533 /* Device mode LPM Accept Control */ 534 #define USB_DWC2_GLPMCFG_LPM_ACK_BULK_POS 23UL 535 #define USB_DWC2_GLPMCFG_LPM_ACK_BULK BIT(USB_DWC2_GLPMCFG_LPM_ACK_BULK_POS) 536 #define USB_DWC2_GLPMCFG_LPM_ACK_ISO_POS 22UL 537 #define USB_DWC2_GLPMCFG_LPM_ACK_ISO BIT(USB_DWC2_GLPMCFG_LPM_ACK_ISO_POS) 538 #define USB_DWC2_GLPMCFG_LPM_NYET_CTRL_POS 21UL 539 #define USB_DWC2_GLPMCFG_LPM_NYET_CTRL BIT(USB_DWC2_GLPMCFG_LPM_NYET_CTRL_POS) 540 #define USB_DWC2_GLPMCFG_LPM_ACK_INTR_POS 20UL 541 #define USB_DWC2_GLPMCFG_LPM_ACK_INTR BIT(USB_DWC2_GLPMCFG_LPM_ACK_INTR_POS) 542 #define USB_DWC2_GLPMCFG_L1RESUMEOK_POS 16UL 543 #define USB_DWC2_GLPMCFG_L1RESUMEOK BIT(USB_DWC2_GLPMCFG_L1RESUMEOK_POS) 544 #define USB_DWC2_GLPMCFG_SLPSTS_POS 15UL 545 #define USB_DWC2_GLPMCFG_SLPSTS BIT(USB_DWC2_GLPMCFG_SLPSTS_POS) 546 #define USB_DWC2_GLPMCFG_COREL1RES_POS 13UL 547 #define USB_DWC2_GLPMCFG_COREL1RES_MASK (0x3UL << USB_DWC2_GLPMCFG_COREL1RES_POS) 548 #define USB_DWC2_GLPMCFG_COREL1RES_ERROR 0 549 #define USB_DWC2_GLPMCFG_COREL1RES_STALL 1 550 #define USB_DWC2_GLPMCFG_COREL1RES_NYET 2 551 #define USB_DWC2_GLPMCFG_COREL1RES_ACK 3 552 #define USB_DWC2_GLPMCFG_HIRD_THRES_POS 8UL 553 #define USB_DWC2_GLPMCFG_HIRD_THRES_MASK (0x1FUL << USB_DWC2_GLPMCFG_HIRD_THRES_POS) 554 #define USB_DWC2_GLPMCFG_ENBLSLPM_POS 7UL 555 #define USB_DWC2_GLPMCFG_ENBLSLPM BIT(USB_DWC2_GLPMCFG_ENBLSLPM_POS) 556 #define USB_DWC2_GLPMCFG_BREMOTEWAKE_POS 6UL 557 #define USB_DWC2_GLPMCFG_BREMOTEWAKE BIT(USB_DWC2_GLPMCFG_BREMOTEWAKE_POS) 558 #define USB_DWC2_GLPMCFG_HIRD_POS 2UL 559 #define USB_DWC2_GLPMCFG_HIRD_MASK (0xFUL << USB_DWC2_GLPMCFG_HIRD_POS) 560 #define USB_DWC2_GLPMCFG_APPL1RES_POS 1UL 561 #define USB_DWC2_GLPMCFG_APPL1RES BIT(USB_DWC2_GLPMCFG_APPL1RES_POS) 562 #define USB_DWC2_GLPMCFG_LPMCAP_POS 0UL 563 #define USB_DWC2_GLPMCFG_LPMCAP BIT(USB_DWC2_GLPMCFG_LPMCAP_POS) 564 565 USB_DWC2_GET_FIELD_DEFINE(glpmcfg_lpm_retrycnt_sts, GLPMCFG_LPM_RETRYCNT_STS) 566 USB_DWC2_GET_FIELD_DEFINE(glpmcfg_lpm_retry_cnt, GLPMCFG_LPM_RETRY_CNT) 567 USB_DWC2_GET_FIELD_DEFINE(glpmcfg_lpm_chnl_indx, GLPMCFG_LPM_CHNL_INDX) 568 USB_DWC2_GET_FIELD_DEFINE(glpmcfg_corel1res, GLPMCFG_COREL1RES) 569 USB_DWC2_GET_FIELD_DEFINE(glpmcfg_hird_thres, GLPMCFG_HIRD_THRES) 570 USB_DWC2_GET_FIELD_DEFINE(glpmcfg_hird, GLPMCFG_HIRD) 571 USB_DWC2_SET_FIELD_DEFINE(glpmcfg_lpm_retry_cnt, GLPMCFG_LPM_RETRY_CNT) 572 USB_DWC2_SET_FIELD_DEFINE(glpmcfg_lpm_chnl_indx, GLPMCFG_LPM_CHNL_INDX) 573 USB_DWC2_SET_FIELD_DEFINE(glpmcfg_hird_thres, GLPMCFG_HIRD_THRES) 574 USB_DWC2_SET_FIELD_DEFINE(glpmcfg_hird, GLPMCFG_HIRD) 575 576 /* Global Power Down Register */ 577 #define USB_DWC2_GPWRDN 0x0058UL 578 #define USB_DWC2_GPWRDN_MULTVALIDBC_POS 24UL 579 #define USB_DWC2_GPWRDN_MULTVALIDBC_MASK (0x1FUL << USB_DWC2_GPWRDN_MULTVALIDBC_POS) 580 #define USB_DWC2_GPWRDN_MULTVALIDBC_RID_0 0 581 #define USB_DWC2_GPWRDN_MULTVALIDBC_RID_C 1 582 #define USB_DWC2_GPWRDN_MULTVALIDBC_RID_B 2 583 #define USB_DWC2_GPWRDN_MULTVALIDBC_RID_A 4 584 #define USB_DWC2_GPWRDN_MULTVALIDBC_RID_GND 8 585 #define USB_DWC2_GPWRDN_MULTVALIDBC_RID_A_GND 12 586 #define USB_DWC2_GPWRDN_MULTVALIDBC_RID_FLOAT 16 587 #define USB_DWC2_GPWRDN_MULTVALIDBC_RID_C_FLOAT 17 588 #define USB_DWC2_GPWRDN_MULTVALIDBC_RID_B_FLOAT 18 589 #define USB_DWC2_GPWRDN_MULTVALIDBC_RID_1 31 590 #define USB_DWC2_GPWRDN_BSESSVLD_POS 22UL 591 #define USB_DWC2_GPWRDN_BSESSVLD BIT(USB_DWC2_GPWRDN_BSESSVLD_POS) 592 #define USB_DWC2_GPWRDN_IDDIG_POS 21UL 593 #define USB_DWC2_GPWRDN_IDDIG BIT(USB_DWC2_GPWRDN_IDDIG_POS) 594 #define USB_DWC2_GPWRDN_LINESTATE_POS 19UL 595 #define USB_DWC2_GPWRDN_LINESTATE_MASK (0x3UL << USB_DWC2_GPWRDN_LINESTATE_POS) 596 #define USB_DWC2_GPWRDN_LINESTATE_DM0DP0 0 597 #define USB_DWC2_GPWRDN_LINESTATE_DM0DP1 1 598 #define USB_DWC2_GPWRDN_LINESTATE_DM1DP0 2 599 #define USB_DWC2_GPWRDN_LINESTATE_NOT_DEFINED 3 600 #define USB_DWC2_GPWRDN_STSCHNGINTMSK_POS 18UL 601 #define USB_DWC2_GPWRDN_STSCHNGINTMSK BIT(USB_DWC2_GPWRDN_STSCHNGINTMSK_POS) 602 #define USB_DWC2_GPWRDN_STSCHNGINT_POS 17UL 603 #define USB_DWC2_GPWRDN_STSCHNGINT BIT(USB_DWC2_GPWRDN_STSCHNGINT_POS) 604 #define USB_DWC2_GPWRDN_SRPDETECTMSK_POS 16UL 605 #define USB_DWC2_GPWRDN_SRPDETECTMSK BIT(USB_DWC2_GPWRDN_SRPDETECTMSK_POS) 606 #define USB_DWC2_GPWRDN_SRPDETECT_POS 15UL 607 #define USB_DWC2_GPWRDN_SRPDETECT BIT(USB_DWC2_GPWRDN_SRPDETECT_POS) 608 #define USB_DWC2_GPWRDN_CONNDETMSK_POS 14UL 609 #define USB_DWC2_GPWRDN_CONNDETMSK BIT(USB_DWC2_GPWRDN_CONNDETMSK_POS) 610 #define USB_DWC2_GPWRDN_CONNECTDET_POS 13UL 611 #define USB_DWC2_GPWRDN_CONNECTDET BIT(USB_DWC2_GPWRDN_CONNECTDET_POS) 612 #define USB_DWC2_GPWRDN_DISCONNECTDETECTMSK_POS 12UL 613 #define USB_DWC2_GPWRDN_DISCONNECTDETECTMSK BIT(USB_DWC2_GPWRDN_DISCONNECTDETECTMSK_POS) 614 #define USB_DWC2_GPWRDN_DISCONNECTDETECT_POS 11UL 615 #define USB_DWC2_GPWRDN_DISCONNECTDETECT BIT(USB_DWC2_GPWRDN_DISCONNECTDETECT_POS) 616 #define USB_DWC2_GPWRDN_RESETDETMSK_POS 10UL 617 #define USB_DWC2_GPWRDN_RESETDETMSK BIT(USB_DWC2_GPWRDN_RESETDETMSK_POS) 618 #define USB_DWC2_GPWRDN_RESETDETECTED_POS 9UL 619 #define USB_DWC2_GPWRDN_RESETDETECTED BIT(USB_DWC2_GPWRDN_RESETDETECTED_POS) 620 #define USB_DWC2_GPWRDN_LINESTAGECHANGEMSK_POS 8UL 621 #define USB_DWC2_GPWRDN_LINESTAGECHANGEMSK BIT(USB_DWC2_GPWRDN_LINESTAGECHANGEMSK_POS) 622 #define USB_DWC2_GPWRDN_LNSTSCHNG_POS 7UL 623 #define USB_DWC2_GPWRDN_LNSTSCHNG BIT(USB_DWC2_GPWRDN_LNSTSCHNG_POS) 624 #define USB_DWC2_GPWRDN_DISABLEVBUS_POS 6UL 625 #define USB_DWC2_GPWRDN_DISABLEVBUS BIT(USB_DWC2_GPWRDN_DISABLEVBUS_POS) 626 #define USB_DWC2_GPWRDN_PWRDNSWTCH_POS 5UL 627 #define USB_DWC2_GPWRDN_PWRDNSWTCH BIT(USB_DWC2_GPWRDN_PWRDNSWTCH_POS) 628 #define USB_DWC2_GPWRDN_PWRDNRST_N_POS 4UL 629 #define USB_DWC2_GPWRDN_PWRDNRST_N BIT(USB_DWC2_GPWRDN_PWRDNRST_N_POS) 630 #define USB_DWC2_GPWRDN_PWRDNCLMP_POS 3UL 631 #define USB_DWC2_GPWRDN_PWRDNCLMP BIT(USB_DWC2_GPWRDN_PWRDNCLMP_POS) 632 #define USB_DWC2_GPWRDN_RESTORE_POS 2UL 633 #define USB_DWC2_GPWRDN_RESTORE BIT(USB_DWC2_GPWRDN_RESTORE_POS) 634 #define USB_DWC2_GPWRDN_PMUACTV_POS 1UL 635 #define USB_DWC2_GPWRDN_PMUACTV BIT(USB_DWC2_GPWRDN_PMUACTV_POS) 636 #define USB_DWC2_GPWRDN_PMUINTSEL_POS 0UL 637 #define USB_DWC2_GPWRDN_PMUINTSEL BIT(USB_DWC2_GPWRDN_PMUINTSEL_POS) 638 639 USB_DWC2_GET_FIELD_DEFINE(gpwrdn_multvalidbc, GPWRDN_MULTVALIDBC) 640 USB_DWC2_GET_FIELD_DEFINE(gpwrdn_linestate, GPWRDN_LINESTATE) 641 642 /* GDFIFOCFG register */ 643 #define USB_DWC2_GDFIFOCFG 0x005CUL 644 #define USB_DWC2_GDFIFOCFG_EPINFOBASEADDR_POS 16UL 645 #define USB_DWC2_GDFIFOCFG_EPINFOBASEADDR_MASK (0xFFFFUL << USB_DWC2_GDFIFOCFG_EPINFOBASEADDR_POS) 646 #define USB_DWC2_GDFIFOCFG_GDFIFOCFG_POS 0UL 647 #define USB_DWC2_GDFIFOCFG_GDFIFOCFG_MASK (0xFFFFUL << USB_DWC2_GDFIFOCFG_GDFIFOCFG_POS) 648 649 USB_DWC2_GET_FIELD_DEFINE(gdfifocfg_epinfobaseaddr, GDFIFOCFG_EPINFOBASEADDR) 650 USB_DWC2_GET_FIELD_DEFINE(gdfifocfg_gdfifocfg, GDFIFOCFG_GDFIFOCFG) 651 USB_DWC2_SET_FIELD_DEFINE(gdfifocfg_epinfobaseaddr, GDFIFOCFG_EPINFOBASEADDR) 652 USB_DWC2_SET_FIELD_DEFINE(gdfifocfg_gdfifocfg, GDFIFOCFG_GDFIFOCFG) 653 654 /* Device IN endpoint transmit FIFO size register */ 655 #define USB_DWC2_DIEPTXF1 0x0104UL 656 #define USB_DWC2_DIEPTXF_INEPNTXFDEP_POS 16UL 657 #define USB_DWC2_DIEPTXF_INEPNTXFDEP_MASK (0xFFFFUL << USB_DWC2_DIEPTXF_INEPNTXFDEP_POS) 658 #define USB_DWC2_DIEPTXF_INEPNTXFSTADDR_POS 0UL 659 #define USB_DWC2_DIEPTXF_INEPNTXFSTADDR_MASK (0xFFFFUL << USB_DWC2_DIEPTXF_INEPNTXFSTADDR_POS) 660 661 USB_DWC2_GET_FIELD_DEFINE(dieptxf_inepntxfdep, DIEPTXF_INEPNTXFDEP) 662 USB_DWC2_GET_FIELD_DEFINE(dieptxf_inepntxfstaddr, DIEPTXF_INEPNTXFSTADDR) 663 USB_DWC2_SET_FIELD_DEFINE(dieptxf_inepntxfdep, DIEPTXF_INEPNTXFDEP) 664 USB_DWC2_SET_FIELD_DEFINE(dieptxf_inepntxfstaddr, DIEPTXF_INEPNTXFSTADDR) 665 666 /* Device configuration registers */ 667 #define USB_DWC2_DCFG 0x0800UL 668 #define USB_DWC2_DCFG_RESVALID_POS 26UL 669 #define USB_DWC2_DCFG_RESVALID_MASK (0x3FUL << USB_DWC2_DCFG_RESVALID_POS) 670 #define USB_DWC2_DCFG_PERSCHINTVL_POS 24UL 671 #define USB_DWC2_DCFG_PERSCHINTVL_MASK (0x3UL << USB_DWC2_DCFG_PERSCHINTVL_POS) 672 #define USB_DWC2_DCFG_PERSCHINTVL_MF25 0 673 #define USB_DWC2_DCFG_PERSCHINTVL_MF50 1 674 #define USB_DWC2_DCFG_PERSCHINTVL_MF75 2 675 #define USB_DWC2_DCFG_PERSCHINTVL_RESERVED 3 676 #define USB_DWC2_DCFG_DESCDMA_POS 23UL 677 #define USB_DWC2_DCFG_DESCDMA BIT(USB_DWC2_DCFG_DESCDMA_POS) 678 #define USB_DWC2_DCFG_EPMISCNT_POS 18UL 679 #define USB_DWC2_DCFG_EPMISCNT_MASK (0x1FUL << USB_DWC2_DCFG_EPMISCNT_POS) 680 #define USB_DWC2_DCFG_IPGISOCSUPT_POS 17UL 681 #define USB_DWC2_DCFG_IPGISOCSUPT BIT(USB_DWC2_DCFG_IPGISOCSUPT_POS) 682 #define USB_DWC2_DCFG_ERRATICINTMSK_POS 15UL 683 #define USB_DWC2_DCFG_ERRATICINTMSK BIT(USB_DWC2_DCFG_ERRATICINTMSK_POS) 684 #define USB_DWC2_DCFG_XCVRDLY_POS 14UL 685 #define USB_DWC2_DCFG_XCVRDLY BIT(USB_DWC2_DCFG_XCVRDLY_POS) 686 #define USB_DWC2_DCFG_ENDEVOUTNAK_POS 13UL 687 #define USB_DWC2_DCFG_ENDEVOUTNAK BIT(USB_DWC2_DCFG_ENDEVOUTNAK_POS) 688 #define USB_DWC2_DCFG_PERFRINT_POS 11UL 689 #define USB_DWC2_DCFG_PERFRINT_MASK (0x3UL << USB_DWC2_DCFG_PERFRINT_POS) 690 #define USB_DWC2_DCFG_PERFRINT_EOPF80 0 691 #define USB_DWC2_DCFG_PERFRINT_EOPF85 1 692 #define USB_DWC2_DCFG_PERFRINT_EOPF90 2 693 #define USB_DWC2_DCFG_PERFRINT_EOPF95 3 694 #define USB_DWC2_DCFG_DEVADDR_POS 4UL 695 #define USB_DWC2_DCFG_DEVADDR_MASK (0x7FUL << USB_DWC2_DCFG_DEVADDR_POS) 696 #define USB_DWC2_DCFG_ENA32KHZSUSP_POS 3UL 697 #define USB_DWC2_DCFG_ENA32KHZSUSP BIT(USB_DWC2_DCFG_ENA32KHZSUSP_POS) 698 #define USB_DWC2_DCFG_NZSTSOUTHSHK_POS 2UL 699 #define USB_DWC2_DCFG_NZSTSOUTHSHK BIT(USB_DWC2_DCFG_NZSTSOUTHSHK_POS) 700 #define USB_DWC2_DCFG_DEVSPD_POS 0UL 701 #define USB_DWC2_DCFG_DEVSPD_MASK (0x03UL << USB_DWC2_DCFG_DEVSPD_POS) 702 #define USB_DWC2_DCFG_DEVSPD_USBHS20 0 703 #define USB_DWC2_DCFG_DEVSPD_USBFS20 1 704 #define USB_DWC2_DCFG_DEVSPD_USBLS116 2 705 #define USB_DWC2_DCFG_DEVSPD_USBFS1148 3 706 707 USB_DWC2_SET_FIELD_DEFINE(dcfg_resvalid, DCFG_RESVALID) 708 USB_DWC2_SET_FIELD_DEFINE(dcfg_perschintvl, DCFG_PERSCHINTVL) 709 USB_DWC2_SET_FIELD_DEFINE(dcfg_epmiscnt, DCFG_EPMISCNT) 710 USB_DWC2_SET_FIELD_DEFINE(dcfg_perfrint, DCFG_PERFRINT) 711 USB_DWC2_SET_FIELD_DEFINE(dcfg_devaddr, DCFG_DEVADDR) 712 USB_DWC2_SET_FIELD_DEFINE(dcfg_devspd, DCFG_DEVSPD) 713 USB_DWC2_GET_FIELD_DEFINE(dcfg_resvalid, DCFG_RESVALID) 714 USB_DWC2_GET_FIELD_DEFINE(dcfg_perschintvl, DCFG_PERSCHINTVL) 715 USB_DWC2_GET_FIELD_DEFINE(dcfg_epmiscnt, DCFG_EPMISCNT) 716 USB_DWC2_GET_FIELD_DEFINE(dcfg_perfrint, DCFG_PERFRINT) 717 USB_DWC2_GET_FIELD_DEFINE(dcfg_devaddr, DCFG_DEVADDR) 718 USB_DWC2_GET_FIELD_DEFINE(dcfg_devspd, DCFG_DEVSPD) 719 720 /* Device control register */ 721 #define USB_DWC2_DCTL 0x0804UL 722 #define USB_DWC2_DCTL_SERVINT_POS 19UL 723 #define USB_DWC2_DCTL_SERVINT BIT(USB_DWC2_DCTL_SERVINT_POS) 724 #define USB_DWC2_DCTL_DEEPSLEEPBESLREJECT_POS 18UL 725 #define USB_DWC2_DCTL_DEEPSLEEPBESLREJECT BIT(USB_DWC2_DCTL_DEEPSLEEPBESLREJECT_POS) 726 #define USB_DWC2_DCTL_NAKONBBLE_POS 16UL 727 #define USB_DWC2_DCTL_NAKONBBLE BIT(USB_DWC2_DCTL_NAKONBBLE_POS) 728 #define USB_DWC2_DCTL_IGNRFRMNUM_POS 15UL 729 #define USB_DWC2_DCTL_IGNRFRMNUM BIT(USB_DWC2_DCTL_IGNRFRMNUM_POS) 730 #define USB_DWC2_DCTL_PWRONPRGDONE_POS 11UL 731 #define USB_DWC2_DCTL_PWRONPRGDONE BIT(USB_DWC2_DCTL_PWRONPRGDONE_POS) 732 #define USB_DWC2_DCTL_CGOUTNAK_POS 10UL 733 #define USB_DWC2_DCTL_CGOUTNAK BIT(USB_DWC2_DCTL_CGOUTNAK_POS) 734 #define USB_DWC2_DCTL_SGOUTNAK_POS 9UL 735 #define USB_DWC2_DCTL_SGOUTNAK BIT(USB_DWC2_DCTL_SGOUTNAK_POS) 736 #define USB_DWC2_DCTL_CGNPINNAK_POS 8UL 737 #define USB_DWC2_DCTL_CGNPINNAK BIT(USB_DWC2_DCTL_CGNPINNAK_POS) 738 #define USB_DWC2_DCTL_SGNPINNAK_POS 7UL 739 #define USB_DWC2_DCTL_SGNPINNAK BIT(USB_DWC2_DCTL_SGNPINNAK_POS) 740 #define USB_DWC2_DCTL_TSTCTL_POS 4UL 741 #define USB_DWC2_DCTL_TSTCTL_MASK (0x7UL << USB_DWC2_DCTL_TSTCTL_POS) 742 #define USB_DWC2_DCTL_TSTCTL_TESTFE 5UL 743 #define USB_DWC2_DCTL_TSTCTL_TESTPM 4UL 744 #define USB_DWC2_DCTL_TSTCTL_TESTSN 3UL 745 #define USB_DWC2_DCTL_TSTCTL_TESTK 2UL 746 #define USB_DWC2_DCTL_TSTCTL_TESTJ 1UL 747 #define USB_DWC2_DCTL_TSTCTL_DISABLED 0UL 748 #define USB_DWC2_DCTL_GOUTNAKSTS_POS 3UL 749 #define USB_DWC2_DCTL_GOUTNAKSTS BIT(USB_DWC2_DCTL_GOUTNAKSTS_POS) 750 #define USB_DWC2_DCTL_GNPINNAKSTS_POS 2UL 751 #define USB_DWC2_DCTL_GNPINNAKSTS BIT(USB_DWC2_DCTL_GNPINNAKSTS_POS) 752 #define USB_DWC2_DCTL_SFTDISCON_POS 1UL 753 #define USB_DWC2_DCTL_SFTDISCON BIT(USB_DWC2_DCTL_SFTDISCON_POS) 754 #define USB_DWC2_DCTL_RMTWKUPSIG_POS 0UL 755 #define USB_DWC2_DCTL_RMTWKUPSIG BIT(USB_DWC2_DCTL_RMTWKUPSIG_POS) 756 757 USB_DWC2_GET_FIELD_DEFINE(dctl_tstctl, DCTL_TSTCTL) 758 USB_DWC2_SET_FIELD_DEFINE(dctl_tstctl, DCTL_TSTCTL) 759 760 /* Device status register */ 761 #define USB_DWC2_DSTS 0x0808UL 762 #define USB_DWC2_DSTS_DEVLNSTS_POS 22UL 763 #define USB_DWC2_DSTS_DEVLNSTS_MASK (0x3UL << USB_DWC2_DSTS_DEVLNSTS_POS) 764 #define USB_DWC2_DSTS_SOFFN_POS 8UL 765 #define USB_DWC2_DSTS_SOFFN_MASK (0x3FFFUL << USB_DWC2_DSTS_SOFFN_POS) 766 #define USB_DWC2_DSTS_ERRTICERR_POS 3UL 767 #define USB_DWC2_DSTS_ERRTICERR BIT(USB_DWC2_DSTS_ERRTICERR_POS) 768 #define USB_DWC2_DSTS_ENUMSPD_POS 1UL 769 #define USB_DWC2_DSTS_ENUMSPD_MASK (0x3UL << USB_DWC2_DSTS_ENUMSPD_POS) 770 #define USB_DWC2_DSTS_ENUMSPD_HS3060 0 771 #define USB_DWC2_DSTS_ENUMSPD_FS3060 1 772 #define USB_DWC2_DSTS_ENUMSPD_LS6 2 773 #define USB_DWC2_DSTS_ENUMSPD_FS48 3 774 #define USB_DWC2_DSTS_SUSPSTS_POS 0UL 775 #define USB_DWC2_DSTS_SUSPSTS BIT(USB_DWC2_DSTS_SUSPSTS_POS) 776 777 USB_DWC2_GET_FIELD_DEFINE(dsts_devlnsts, DSTS_DEVLNSTS) 778 USB_DWC2_GET_FIELD_DEFINE(dsts_soffn, DSTS_SOFFN) 779 USB_DWC2_GET_FIELD_DEFINE(dsts_enumspd, DSTS_ENUMSPD) 780 781 /* Device all endpoints interrupt registers */ 782 #define USB_DWC2_DAINT 0x0818UL 783 #define USB_DWC2_DAINTMSK 0x081CUL 784 #define USB_DWC2_DAINT_OUTEPINT(ep_num) BIT(16UL + ep_num) 785 #define USB_DWC2_DAINT_INEPINT(ep_num) BIT(ep_num) 786 787 /* Device threshold control register */ 788 #define USB_DWC2_DTHRCTL 0x0830UL 789 #define USB_DWC2_DTHRCTL_ARBPRKEN_POS 27UL 790 #define USB_DWC2_DTHRCTL_ARBPRKEN BIT(USB_DWC2_DTHRCTL_ARBPRKEN_POS) 791 #define USB_DWC2_DTHRCTL_RXTHRLEN_POS 17UL 792 #define USB_DWC2_DTHRCTL_RXTHRLEN_MASK (0x1FFUL << USB_DWC2_DTHRCTL_RXTHRLEN_POS) 793 #define USB_DWC2_DTHRCTL_RXTHREN_POS 16UL 794 #define USB_DWC2_DTHRCTL_RXTHREN BIT(USB_DWC2_DTHRCTL_RXTHREN_POS) 795 #define USB_DWC2_DTHRCTL_AHBTHRRATIO_POS 11UL 796 #define USB_DWC2_DTHRCTL_AHBTHRRATIO_MASK (0x3UL << USB_DWC2_DTHRCTL_AHBTHRRATIO_POS) 797 #define USB_DWC2_DTHRCTL_AHBTHRRATIO_THRESZERO 0 798 #define USB_DWC2_DTHRCTL_AHBTHRRATIO_THRESONE 1 799 #define USB_DWC2_DTHRCTL_AHBTHRRATIO_THRESTWO 2 800 #define USB_DWC2_DTHRCTL_AHBTHRRATIO_THRESTHREE 3 801 #define USB_DWC2_DTHRCTL_TXTHRLEN_POS 2UL 802 #define USB_DWC2_DTHRCTL_TXTHRLEN_MASK (0x1FFUL << USB_DWC2_DTHRCTL_TXTHRLEN_POS) 803 #define USB_DWC2_DTHRCTL_ISOTHREN_POS 1UL 804 #define USB_DWC2_DTHRCTL_ISOTHREN BIT(USB_DWC2_DTHRCTL_ISOTHREN_POS) 805 #define USB_DWC2_DTHRCTL_NONISOTHREN_POS 0UL 806 #define USB_DWC2_DTHRCTL_NONISOTHREN BIT(USB_DWC2_DTHRCTL_NONISOTHREN_POS) 807 808 USB_DWC2_GET_FIELD_DEFINE(dthrctl_rxthrlen, DTHRCTL_RXTHRLEN) 809 USB_DWC2_GET_FIELD_DEFINE(dthrctl_ahbthrratio, DTHRCTL_AHBTHRRATIO) 810 USB_DWC2_GET_FIELD_DEFINE(dthrctl_txthrlen, DTHRCTL_TXTHRLEN) 811 USB_DWC2_SET_FIELD_DEFINE(dthrctl_rxthrlen, DTHRCTL_RXTHRLEN) 812 USB_DWC2_SET_FIELD_DEFINE(dthrctl_ahbthrratio, DTHRCTL_AHBTHRRATIO) 813 USB_DWC2_SET_FIELD_DEFINE(dthrctl_txthrlen, DTHRCTL_TXTHRLEN) 814 815 /* 816 * Device IN/OUT endpoint control register 817 * IN endpoint offsets 0x0900 + (0x20 * n), n = 0 .. x, 818 * OUT endpoint offsets 0x0B00 + (0x20 * n), n = 0 .. x, 819 * 820 */ 821 #define USB_DWC2_DIEPCTL0 0x0900UL 822 #define USB_DWC2_DOEPCTL0 0x0B00UL 823 #define USB_DWC2_DEPCTL_EPENA_POS 31UL 824 #define USB_DWC2_DEPCTL_EPENA BIT(USB_DWC2_DEPCTL_EPENA_POS) 825 #define USB_DWC2_DEPCTL_EPDIS_POS 30UL 826 #define USB_DWC2_DEPCTL_EPDIS BIT(USB_DWC2_DEPCTL_EPDIS_POS) 827 #define USB_DWC2_DEPCTL_SETD1PID_POS 29UL 828 #define USB_DWC2_DEPCTL_SETD1PID BIT(USB_DWC2_DEPCTL_SETD1PID_POS) 829 #define USB_DWC2_DEPCTL_SETODDFR USB_DWC2_DEPCTL_SETD1PID 830 #define USB_DWC2_DEPCTL_SETD0PID_POS 28UL 831 #define USB_DWC2_DEPCTL_SETD0PID BIT(USB_DWC2_DEPCTL_SETD0PID_POS) 832 #define USB_DWC2_DEPCTL_SETEVENFR USB_DWC2_DEPCTL_SETD0PID 833 #define USB_DWC2_DEPCTL_SNAK_POS 27UL 834 #define USB_DWC2_DEPCTL_SNAK BIT(USB_DWC2_DEPCTL_SNAK_POS) 835 #define USB_DWC2_DEPCTL_CNAK_POS 26UL 836 #define USB_DWC2_DEPCTL_CNAK BIT(USB_DWC2_DEPCTL_CNAK_POS) 837 #define USB_DWC2_DEPCTL_TXFNUM_POS 22UL 838 #define USB_DWC2_DEPCTL_TXFNUM_MASK (0xFUL << USB_DWC2_DEPCTL_TXFNUM_POS) 839 #define USB_DWC2_DEPCTL_STALL_POS 21UL 840 #define USB_DWC2_DEPCTL_STALL BIT(USB_DWC2_DEPCTL_STALL_POS) 841 #define USB_DWC2_DEPCTL_EPTYPE_POS 18UL 842 #define USB_DWC2_DEPCTL_EPTYPE_MASK (0x3UL << USB_DWC2_DEPCTL_EPTYPE_POS) 843 #define USB_DWC2_DEPCTL_EPTYPE_INTERRUPT 3 844 #define USB_DWC2_DEPCTL_EPTYPE_BULK 2 845 #define USB_DWC2_DEPCTL_EPTYPE_ISO 1 846 #define USB_DWC2_DEPCTL_EPTYPE_CONTROL 0 847 #define USB_DWC2_DEPCTL_NAKSTS_POS 17UL 848 #define USB_DWC2_DEPCTL_NAKSTS BIT(USB_DWC2_DEPCTL_NAKSTS_POS) 849 #define USB_DWC2_DEPCTL_DPID_POS 16UL 850 #define USB_DWC2_DEPCTL_DPID BIT(USB_DWC2_DEPCTL_DPID_POS) 851 #define USB_DWC2_DEPCTL_USBACTEP_POS 15UL 852 #define USB_DWC2_DEPCTL_USBACTEP BIT(USB_DWC2_DEPCTL_USBACTEP_POS) 853 #define USB_DWC2_DEPCTL0_MPS_POS 0UL 854 #define USB_DWC2_DEPCTL0_MPS_MASK (0x3UL << USB_DWC2_DEPCTL0_MPS_POS) 855 #define USB_DWC2_DEPCTL0_MPS_8 3 856 #define USB_DWC2_DEPCTL0_MPS_16 2 857 #define USB_DWC2_DEPCTL0_MPS_32 1 858 #define USB_DWC2_DEPCTL0_MPS_64 0 859 #define USB_DWC2_DEPCTL_MPS_POS 0UL 860 #define USB_DWC2_DEPCTL_MPS_MASK (0x7FF << USB_DWC2_DEPCTL_MPS_POS) 861 862 USB_DWC2_GET_FIELD_DEFINE(depctl_txfnum, DEPCTL_TXFNUM) 863 USB_DWC2_SET_FIELD_DEFINE(depctl_txfnum, DEPCTL_TXFNUM) 864 USB_DWC2_GET_FIELD_DEFINE(depctl_eptype, DEPCTL_EPTYPE) 865 USB_DWC2_SET_FIELD_DEFINE(depctl_eptype, DEPCTL_EPTYPE) 866 USB_DWC2_GET_FIELD_DEFINE(depctl0_mps, DEPCTL0_MPS) 867 USB_DWC2_SET_FIELD_DEFINE(depctl0_mps, DEPCTL0_MPS) 868 USB_DWC2_GET_FIELD_DEFINE(depctl_mps, DEPCTL_MPS) 869 USB_DWC2_SET_FIELD_DEFINE(depctl_mps, DEPCTL_MPS) 870 871 /* 872 * Device IN endpoint interrupt register 873 * offsets 0x0908 + (0x20 * n), n = 0 .. x 874 */ 875 #define USB_DWC2_DIEPINT0 0x0908UL 876 #define USB_DWC2_DIEPINT_NYETINTRPT_POS 14UL 877 #define USB_DWC2_DIEPINT_NYETINTRPT BIT(USB_DWC2_DIEPINT_NYETINTRPT_POS) 878 #define USB_DWC2_DIEPINT_NAKINTRPT_POS 13UL 879 #define USB_DWC2_DIEPINT_NAKINTRPT BIT(USB_DWC2_DIEPINT_NAKINTRPT_POS) 880 #define USB_DWC2_DIEPINT_BBLEERR_POS 12UL 881 #define USB_DWC2_DIEPINT_BBLEERR BIT(USB_DWC2_DIEPINT_BBLEERR_POS) 882 #define USB_DWC2_DIEPINT_PKTDRPSTS_POS 11UL 883 #define USB_DWC2_DIEPINT_PKTDRPSTS BIT(USB_DWC2_DIEPINT_PKTDRPSTS_POS) 884 #define USB_DWC2_DIEPINT_BNAINTR_POS 9UL 885 #define USB_DWC2_DIEPINT_BNAINTR BIT(USB_DWC2_DIEPINT_BNAINTR_POS) 886 #define USB_DWC2_DIEPINT_TXFIFOUNDRN_POS 8UL 887 #define USB_DWC2_DIEPINT_TXFIFOUNDRN BIT(USB_DWC2_DIEPINT_TXFIFOUNDRN_POS) 888 #define USB_DWC2_DIEPINT_TXFEMP_POS 7UL 889 #define USB_DWC2_DIEPINT_TXFEMP BIT(USB_DWC2_DIEPINT_TXFEMP_POS) 890 #define USB_DWC2_DIEPINT_INEPNAKEFF_POS 6UL 891 #define USB_DWC2_DIEPINT_INEPNAKEFF BIT(USB_DWC2_DIEPINT_INEPNAKEFF_POS) 892 #define USB_DWC2_DIEPINT_INTKNEPMIS_POS 5UL 893 #define USB_DWC2_DIEPINT_INTKNEPMIS BIT(USB_DWC2_DIEPINT_INTKNEPMIS_POS) 894 #define USB_DWC2_DIEPINT_INTKNTXFEMP_POS 4UL 895 #define USB_DWC2_DIEPINT_INTKNTXFEMP BIT(USB_DWC2_DIEPINT_INTKNTXFEMP_POS) 896 #define USB_DWC2_DIEPINT_TIMEOUT_POS 3UL 897 #define USB_DWC2_DIEPINT_TIMEOUT BIT(USB_DWC2_DIEPINT_TIMEOUT_POS) 898 #define USB_DWC2_DIEPINT_AHBERR_POS 2UL 899 #define USB_DWC2_DIEPINT_AHBERR BIT(USB_DWC2_DIEPINT_AHBERR_POS) 900 #define USB_DWC2_DIEPINT_EPDISBLD_POS 1UL 901 #define USB_DWC2_DIEPINT_EPDISBLD BIT(USB_DWC2_DIEPINT_EPDISBLD_POS) 902 #define USB_DWC2_DIEPINT_XFERCOMPL_POS 0UL 903 #define USB_DWC2_DIEPINT_XFERCOMPL BIT(USB_DWC2_DIEPINT_XFERCOMPL_POS) 904 905 /* 906 * Device OUT endpoint interrupt register 907 * offsets 0x0B08 + (0x20 * n), n = 0 .. x 908 */ 909 #define USB_DWC2_DOEPINT0 0x0B08UL 910 #define USB_DWC2_DOEPINT_STUPPKTRCVD_POS 15UL 911 #define USB_DWC2_DOEPINT_STUPPKTRCVD BIT(USB_DWC2_DOEPINT_STUPPKTRCVD_POS) 912 #define USB_DWC2_DOEPINT_NYETINTRPT_POS 14UL 913 #define USB_DWC2_DOEPINT_NYETINTRPT BIT(USB_DWC2_DOEPINT_NYETINTRPT_POS) 914 #define USB_DWC2_DOEPINT_NAKINTRPT_POS 13UL 915 #define USB_DWC2_DOEPINT_NAKINTRPT BIT(USB_DWC2_DOEPINT_NAKINTRPT_POS) 916 #define USB_DWC2_DOEPINT_BBLEERR_POS 12UL 917 #define USB_DWC2_DOEPINT_BBLEERR BIT(USB_DWC2_DOEPINT_BBLEERR_POS) 918 #define USB_DWC2_DOEPINT_PKTDRPSTS_POS 11UL 919 #define USB_DWC2_DOEPINT_PKTDRPSTS BIT(USB_DWC2_DOEPINT_PKTDRPSTS_POS) 920 #define USB_DWC2_DOEPINT_BNAINTR_POS 9UL 921 #define USB_DWC2_DOEPINT_BNAINTR BIT(USB_DWC2_DOEPINT_BNAINTR_POS) 922 #define USB_DWC2_DOEPINT_OUTPKTERR_POS 8UL 923 #define USB_DWC2_DOEPINT_OUTPKTERR BIT(USB_DWC2_DOEPINT_OUTPKTERR_POS) 924 #define USB_DWC2_DOEPINT_BACK2BACKSETUP_POS 6UL 925 #define USB_DWC2_DOEPINT_BACK2BACKSETUP BIT(USB_DWC2_DOEPINT_BACK2BACKSETUP_POS) 926 #define USB_DWC2_DOEPINT_STSPHSERCVD_POS 5UL 927 #define USB_DWC2_DOEPINT_STSPHSERCVD BIT(USB_DWC2_DOEPINT_STSPHSERCVD_POS) 928 #define USB_DWC2_DOEPINT_OUTTKNEPDIS_POS 4UL 929 #define USB_DWC2_DOEPINT_OUTTKNEPDIS BIT(USB_DWC2_DOEPINT_OUTTKNEPDIS_POS) 930 #define USB_DWC2_DOEPINT_SETUP_POS 3UL 931 #define USB_DWC2_DOEPINT_SETUP BIT(USB_DWC2_DOEPINT_SETUP_POS) 932 #define USB_DWC2_DOEPINT_AHBERR_POS 2UL 933 #define USB_DWC2_DOEPINT_AHBERR BIT(USB_DWC2_DOEPINT_AHBERR_POS) 934 #define USB_DWC2_DOEPINT_EPDISBLD_POS 1UL 935 #define USB_DWC2_DOEPINT_EPDISBLD BIT(USB_DWC2_DOEPINT_EPDISBLD_POS) 936 #define USB_DWC2_DOEPINT_XFERCOMPL_POS 0UL 937 #define USB_DWC2_DOEPINT_XFERCOMPL BIT(USB_DWC2_DOEPINT_XFERCOMPL_POS) 938 939 /* Device IN control endpoint transfer size register */ 940 #define USB_DWC2_DIEPTSIZ0 0x0910UL 941 #define USB_DWC2_DIEPTSIZ0_PKTCNT_POS 19UL 942 #define USB_DWC2_DIEPTSIZ0_PKTCNT_MASK (0x3UL << USB_DWC2_DIEPTSIZ0_PKTCNT_POS) 943 #define USB_DWC2_DIEPTSIZ0_XFERSIZE_POS 0UL 944 #define USB_DWC2_DIEPTSIZ0_XFERSIZE_MASK 0x7FUL 945 946 USB_DWC2_GET_FIELD_DEFINE(dieptsiz0_pktcnt, DIEPTSIZ0_PKTCNT) 947 USB_DWC2_GET_FIELD_DEFINE(dieptsiz0_xfersize, DIEPTSIZ0_XFERSIZE) 948 949 /* Device OUT control endpoint transfer size register */ 950 #define USB_DWC2_DOEPTSIZ0 0x0B10UL 951 #define USB_DWC2_DOEPTSIZ0_SUPCNT_POS 29UL 952 #define USB_DWC2_DOEPTSIZ0_SUPCNT_MASK (0x3UL << USB_DWC2_DOEPTSIZ0_SUPCNT_POS) 953 #define USB_DWC2_DOEPTSIZ0_PKTCNT_POS 19UL 954 #define USB_DWC2_DOEPTSIZ0_PKTCNT_MASK (0x1UL << USB_DWC2_DOEPTSIZ0_PKTCNT_POS) 955 #define USB_DWC2_DOEPTSIZ0_XFERSIZE_POS 0UL 956 #define USB_DWC2_DOEPTSIZ0_XFERSIZE_MASK 0x7FUL 957 958 USB_DWC2_GET_FIELD_DEFINE(doeptsiz0_supcnt, DOEPTSIZ0_SUPCNT) 959 USB_DWC2_GET_FIELD_DEFINE(doeptsiz0_pktcnt, DOEPTSIZ0_PKTCNT) 960 USB_DWC2_GET_FIELD_DEFINE(doeptsiz0_xfersize, DOEPTSIZ0_XFERSIZE) 961 962 /* 963 * Device IN endpoint transfer size register 964 * at offsets 0x0910 + (0x20 * n), n = 1 .. x 965 */ 966 #define USB_DWC2_DIEPTSIZN_MC_POS 29UL 967 #define USB_DWC2_DIEPTSIZN_MC_MASK (0x3UL << USB_DWC2_DIEPTSIZN_MC_POS) 968 #define USB_DWC2_DIEPTSIZN_PKTCNT_POS 19UL 969 #define USB_DWC2_DIEPTSIZN_PKTCNT_MASK (0x3FFUL << USB_DWC2_DIEPTSIZN_PKTCNT_POS) 970 #define USB_DWC2_DIEPTSIZN_XFERSIZE_POS 0UL 971 #define USB_DWC2_DIEPTSIZN_XFERSIZE_MASK 0x7FFFFUL 972 973 USB_DWC2_GET_FIELD_DEFINE(dieptsizn_mc, DIEPTSIZN_MC) 974 USB_DWC2_GET_FIELD_DEFINE(dieptsizn_pktcnt, DIEPTSIZN_PKTCNT) 975 USB_DWC2_GET_FIELD_DEFINE(dieptsizn_xfersize, DIEPTSIZN_XFERSIZE) 976 USB_DWC2_SET_FIELD_DEFINE(dieptsizn_mc, DIEPTSIZN_MC) 977 USB_DWC2_SET_FIELD_DEFINE(dieptsizn_pktcnt, DIEPTSIZN_PKTCNT) 978 USB_DWC2_SET_FIELD_DEFINE(dieptsizn_xfersize, DIEPTSIZN_XFERSIZE) 979 980 /* 981 * Device OUT endpoint transfer size register 982 * at offsets 0x0B10 + (0x20 * n), n = 1 .. x 983 */ 984 #define USB_DWC2_DOEPTSIZN_RXDPID_POS 29UL 985 #define USB_DWC2_DOEPTSIZN_RXDPID_MASK (0x3UL << USB_DWC2_DOEPTSIZN_RXDPID_POS) 986 #define USB_DWC2_DOEPTSIZN_RXDPID_MDATA 3 987 #define USB_DWC2_DOEPTSIZN_RXDPID_DATA1 2 988 #define USB_DWC2_DOEPTSIZN_RXDPID_DATA2 1 989 #define USB_DWC2_DOEPTSIZN_RXDPID_DATA0 0 990 #define USB_DWC2_DOEPTSIZN_PKTCNT_POS 19UL 991 #define USB_DWC2_DOEPTSIZN_PKTCNT_MASK (0x3FFUL << USB_DWC2_DOEPTSIZN_PKTCNT_POS) 992 #define USB_DWC2_DOEPTSIZN_XFERSIZE_POS 0UL 993 #define USB_DWC2_DOEPTSIZN_XFERSIZE_MASK 0x7FFFFUL 994 995 USB_DWC2_GET_FIELD_DEFINE(doeptsizn_rxdpid, DOEPTSIZN_RXDPID) 996 USB_DWC2_GET_FIELD_DEFINE(doeptsizn_pktcnt, DOEPTSIZN_PKTCNT) 997 USB_DWC2_GET_FIELD_DEFINE(doeptsizn_xfersize, DOEPTSIZN_XFERSIZE) 998 USB_DWC2_SET_FIELD_DEFINE(doeptsizn_pktcnt, DOEPTSIZN_PKTCNT) 999 USB_DWC2_SET_FIELD_DEFINE(doeptsizn_xfersize, DOEPTSIZN_XFERSIZE) 1000 1001 /* Power and Clock Gating Control Register */ 1002 #define USB_DWC2_PCGCCTL 0x0E00UL 1003 #define USB_DWC2_PCGCCTL_IF_DEV_MODE_POS 31UL 1004 #define USB_DWC2_PCGCCTL_IF_DEV_MODE BIT(USB_DWC2_PCGCCTL_IF_DEV_MODE_POS) 1005 #define USB_DWC2_PCGCCTL_P2HD_PRT_SPD_POS 29UL 1006 #define USB_DWC2_PCGCCTL_P2HD_PRT_SPD_MASK (0x3UL << USB_DWC2_PCGCCTL_P2HD_PRT_SPD_POS) 1007 #define USB_DWC2_PCGCCTL_P2HD_PRT_SPD_LS 2 1008 #define USB_DWC2_PCGCCTL_P2HD_PRT_SPD_FS 1 1009 #define USB_DWC2_PCGCCTL_P2HD_PRT_SPD_HS 0 1010 #define USB_DWC2_PCGCCTL_P2HD_DEV_ENUM_SPD_POS 27UL 1011 #define USB_DWC2_PCGCCTL_P2HD_DEV_ENUM_SPD_MASK (0x3UL << USB_DWC2_PCGCCTL_P2HD_DEV_ENUM_SPD_POS) 1012 #define USB_DWC2_PCGCCTL_P2HD_DEV_ENUM_SPD_FS48 3 1013 #define USB_DWC2_PCGCCTL_P2HD_DEV_ENUM_SPD_LS 2 1014 #define USB_DWC2_PCGCCTL_P2HD_DEV_ENUM_SPD_FS 1 1015 #define USB_DWC2_PCGCCTL_P2HD_DEV_ENUM_SPD_HS 0 1016 #define USB_DWC2_PCGCCTL_MAC_DEV_ADDR_POS 20UL 1017 #define USB_DWC2_PCGCCTL_MAC_DEV_ADDR_MASK (0x7FUL << USB_DWC2_PCGCCTL_MAC_DEV_ADDR_POS) 1018 #define USB_DWC2_PCGCCTL_MAX_TERMSELECT_POS 19UL 1019 #define USB_DWC2_PCGCCTL_MAX_TERMSELECT BIT(USB_DWC2_PCGCCTL_MAX_TERMSELECT_POS) 1020 #define USB_DWC2_PCGCCTL_MAC_XCVRSELECT_POS 17UL 1021 #define USB_DWC2_PCGCCTL_MAC_XCVRSELECT_MASK (0x3UL << USB_DWC2_PCGCCTL_MAC_XCVRSELECT_POS) 1022 #define USB_DWC2_PCGCCTL_MAC_XCVRSELECT_LFS 3 1023 #define USB_DWC2_PCGCCTL_MAC_XCVRSELECT_LS 2 1024 #define USB_DWC2_PCGCCTL_MAC_XCVRSELECT_FS 1 1025 #define USB_DWC2_PCGCCTL_MAC_XCVRSELECT_HS 0 1026 #define USB_DWC2_PCGCCTL_SH2PL_PRT_CTL0_POS 16UL 1027 #define USB_DWC2_PCGCCTL_SH2PL_PRT_CTL0 BIT(USB_DWC2_PCGCCTL_SH2PL_PRT_CTL0_POS) 1028 #define USB_DWC2_PCGCCTL_PRT_CLK_SEL_POS 14UL 1029 #define USB_DWC2_PCGCCTL_PRT_CLK_SEL_MASK (0x3UL << USB_DWC2_PCGCCTL_PRT_CLK_SEL_POS) 1030 #define USB_DWC2_PCGCCTL_RESTOREVALUE_POS 14UL 1031 #define USB_DWC2_PCGCCTL_RESTOREVALUE_MASK (0x3FFFFUL << USB_DWC2_PCGCCTL_RESTOREVALUE_POS) 1032 #define USB_DWC2_PCGCCTL_ESSREGRESTORED_POS 13UL 1033 #define USB_DWC2_PCGCCTL_ESSREGRESTORED BIT(USB_DWC2_PCGCCTL_ESSREGRESTORED_POS) 1034 #define USB_DWC2_PCGCCTL_RESTOREMODE_POS 9UL 1035 #define USB_DWC2_PCGCCTL_RESTOREMODE BIT(USB_DWC2_PCGCCTL_RESTOREMODE_POS) 1036 #define USB_DWC2_PCGCCTL_L1SUSPENDED_POS 7UL 1037 #define USB_DWC2_PCGCCTL_L1SUSPENDED BIT(USB_DWC2_PCGCCTL_L1SUSPENDED_POS) 1038 #define USB_DWC2_PCGCCTL_PHYSLEEP_POS 6UL 1039 #define USB_DWC2_PCGCCTL_PHYSLEEP BIT(USB_DWC2_PCGCCTL_PHYSLEEP_POS) 1040 #define USB_DWC2_PCGCCTL_ENBL_L1GATING_POS 5UL 1041 #define USB_DWC2_PCGCCTL_ENBL_L1GATING BIT(USB_DWC2_PCGCCTL_ENBL_L1GATING_POS) 1042 #define USB_DWC2_PCGCCTL_RSTPDWNMODULE_POS 3UL 1043 #define USB_DWC2_PCGCCTL_RSTPDWNMODULE BIT(USB_DWC2_PCGCCTL_RSTPDWNMODULE_POS) 1044 #define USB_DWC2_PCGCCTL_GATEHCLK_POS 1UL 1045 #define USB_DWC2_PCGCCTL_GATEHCLK BIT(USB_DWC2_PCGCCTL_GATEHCLK_POS) 1046 #define USB_DWC2_PCGCCTL_STOPPCLK_POS 0UL 1047 #define USB_DWC2_PCGCCTL_STOPPCLK BIT(USB_DWC2_PCGCCTL_STOPPCLK_POS) 1048 1049 USB_DWC2_GET_FIELD_DEFINE(pcgcctl_p2hd_prt_spd, PCGCCTL_P2HD_PRT_SPD) 1050 USB_DWC2_GET_FIELD_DEFINE(pcgcctl_p2hd_dev_enum_spd, PCGCCTL_P2HD_DEV_ENUM_SPD) 1051 USB_DWC2_GET_FIELD_DEFINE(pcgcctl_mac_dev_addr, PCGCCTL_MAC_DEV_ADDR) 1052 USB_DWC2_GET_FIELD_DEFINE(pcgcctl_mac_xcvrselect, PCGCCTL_MAC_XCVRSELECT) 1053 USB_DWC2_GET_FIELD_DEFINE(pcgcctl_prt_clk_sel, PCGCCTL_PRT_CLK_SEL) 1054 USB_DWC2_GET_FIELD_DEFINE(pcgcctl_restorevalue, PCGCCTL_RESTOREVALUE) 1055 USB_DWC2_SET_FIELD_DEFINE(pcgcctl_restorevalue, PCGCCTL_RESTOREVALUE) 1056 1057 /* 1058 * Device IN/OUT endpoint transfer size register 1059 * IN at offsets 0x0910 + (0x20 * n), n = 0 .. x, 1060 * OUT at offsets 0x0B10 + (0x20 * n), n = 0 .. x 1061 * 1062 * Note: Legacy definitions for the usb_dc_dw.c driver only. 1063 */ 1064 #define USB_DWC2_DEPTSIZ_PKT_CNT_POS 19UL 1065 #define USB_DWC2_DIEPTSIZ0_PKT_CNT_MASK (0x3 << 19) 1066 #define USB_DWC2_DIEPTSIZn_PKT_CNT_MASK (0x3FF << 19) 1067 #define USB_DWC2_DOEPTSIZn_PKT_CNT_MASK (0x3FF << 19) 1068 #define USB_DWC2_DOEPTSIZ0_PKT_CNT_MASK (0x1 << 19) 1069 #define USB_DWC2_DOEPTSIZ_SUP_CNT_POS 29UL 1070 #define USB_DWC2_DOEPTSIZ_SUP_CNT_MASK (0x3 << 29) 1071 #define USB_DWC2_DEPTSIZ_XFER_SIZE_POS 0UL 1072 #define USB_DWC2_DEPTSIZ0_XFER_SIZE_MASK 0x7F 1073 #define USB_DWC2_DEPTSIZn_XFER_SIZE_MASK 0x7FFFF 1074 1075 /* 1076 * Device IN endpoint transmit FIFO status register, 1077 * offsets 0x0918 + (0x20 * n), n = 0 .. x 1078 */ 1079 #define USB_DWC2_DTXFSTS0 0x0918UL 1080 #define USB_DWC2_DTXFSTS_INEPTXFSPCAVAIL_POS 0UL 1081 #define USB_DWC2_DTXFSTS_INEPTXFSPCAVAIL_MASK 0xFFFFUL 1082 1083 USB_DWC2_GET_FIELD_DEFINE(dtxfsts_ineptxfspcavail, DTXFSTS_INEPTXFSPCAVAIL) 1084 1085 #ifdef __cplusplus 1086 } 1087 #endif 1088 1089 #endif /* ZEPHYR_DRIVERS_USB_COMMON_USB_DWC2_HW */ 1090
