1 /* 2 * Copyright (c) 2024 Silicon Laboratories Inc. 3 * SPDX-License-Identifier: Apache-2.0 4 * 5 * Pin Control for Silicon Labs XG21 devices 6 * 7 * This file was generated by the script gen_pinctrl.py in the hal_silabs module. 8 * Do not manually edit. 9 */ 10 11 #ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG21_PINCTRL_H_ 12 #define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG21_PINCTRL_H_ 13 14 #include <dt-bindings/pinctrl/silabs-pinctrl-dbus.h> 15 16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1) 17 18 #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 1) 19 20 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 10, 1, 0, 2) 21 #define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 10, 1, 1, 3) 22 #define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 10, 1, 2, 4) 23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 10, 0, 0, 1) 24 25 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 17, 1, 0, 1) 26 #define SILABS_DBUS_PTI_DFRAME(port, pin) SILABS_DBUS(port, pin, 17, 1, 1, 2) 27 #define SILABS_DBUS_PTI_DOUT(port, pin) SILABS_DBUS(port, pin, 17, 1, 2, 3) 28 29 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 22, 1, 0, 1) 30 #define SILABS_DBUS_I2C0_SDA(port, pin) SILABS_DBUS(port, pin, 22, 1, 1, 2) 31 32 #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 26, 1, 0, 1) 33 #define SILABS_DBUS_I2C1_SDA(port, pin) SILABS_DBUS(port, pin, 26, 1, 1, 2) 34 35 #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 30, 1, 0, 1) 36 #define SILABS_DBUS_LETIMER0_OUT1(port, pin) SILABS_DBUS(port, pin, 30, 1, 1, 2) 37 38 #define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 34, 1, 0, 1) 39 #define SILABS_DBUS_MODEM_ANT1(port, pin) SILABS_DBUS(port, pin, 34, 1, 1, 2) 40 #define SILABS_DBUS_MODEM_DCLK(port, pin) SILABS_DBUS(port, pin, 34, 1, 2, 3) 41 #define SILABS_DBUS_MODEM_DOUT(port, pin) SILABS_DBUS(port, pin, 34, 1, 3, 5) 42 #define SILABS_DBUS_MODEM_DIN(port, pin) SILABS_DBUS(port, pin, 34, 0, 0, 4) 43 44 #define SILABS_DBUS_PRS0_ASYNCH0(port, pin) SILABS_DBUS(port, pin, 41, 1, 0, 1) 45 #define SILABS_DBUS_PRS0_ASYNCH1(port, pin) SILABS_DBUS(port, pin, 41, 1, 1, 2) 46 #define SILABS_DBUS_PRS0_ASYNCH2(port, pin) SILABS_DBUS(port, pin, 41, 1, 2, 3) 47 #define SILABS_DBUS_PRS0_ASYNCH3(port, pin) SILABS_DBUS(port, pin, 41, 1, 3, 4) 48 #define SILABS_DBUS_PRS0_ASYNCH4(port, pin) SILABS_DBUS(port, pin, 41, 1, 4, 5) 49 #define SILABS_DBUS_PRS0_ASYNCH5(port, pin) SILABS_DBUS(port, pin, 41, 1, 5, 6) 50 #define SILABS_DBUS_PRS0_ASYNCH6(port, pin) SILABS_DBUS(port, pin, 41, 1, 6, 7) 51 #define SILABS_DBUS_PRS0_ASYNCH7(port, pin) SILABS_DBUS(port, pin, 41, 1, 7, 8) 52 #define SILABS_DBUS_PRS0_ASYNCH8(port, pin) SILABS_DBUS(port, pin, 41, 1, 8, 9) 53 #define SILABS_DBUS_PRS0_ASYNCH9(port, pin) SILABS_DBUS(port, pin, 41, 1, 9, 10) 54 #define SILABS_DBUS_PRS0_ASYNCH10(port, pin) SILABS_DBUS(port, pin, 41, 1, 10, 11) 55 #define SILABS_DBUS_PRS0_ASYNCH11(port, pin) SILABS_DBUS(port, pin, 41, 1, 11, 12) 56 #define SILABS_DBUS_PRS0_SYNCH0(port, pin) SILABS_DBUS(port, pin, 41, 1, 12, 13) 57 #define SILABS_DBUS_PRS0_SYNCH1(port, pin) SILABS_DBUS(port, pin, 41, 1, 13, 14) 58 #define SILABS_DBUS_PRS0_SYNCH2(port, pin) SILABS_DBUS(port, pin, 41, 1, 14, 15) 59 #define SILABS_DBUS_PRS0_SYNCH3(port, pin) SILABS_DBUS(port, pin, 41, 1, 15, 16) 60 61 #define SILABS_DBUS_TIMER0_CC0(port, pin) SILABS_DBUS(port, pin, 59, 1, 0, 1) 62 #define SILABS_DBUS_TIMER0_CC1(port, pin) SILABS_DBUS(port, pin, 59, 1, 1, 2) 63 #define SILABS_DBUS_TIMER0_CC2(port, pin) SILABS_DBUS(port, pin, 59, 1, 2, 3) 64 #define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 59, 1, 3, 4) 65 #define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 59, 1, 4, 5) 66 #define SILABS_DBUS_TIMER0_CDTI2(port, pin) SILABS_DBUS(port, pin, 59, 1, 5, 6) 67 68 #define SILABS_DBUS_TIMER1_CC0(port, pin) SILABS_DBUS(port, pin, 67, 1, 0, 1) 69 #define SILABS_DBUS_TIMER1_CC1(port, pin) SILABS_DBUS(port, pin, 67, 1, 1, 2) 70 #define SILABS_DBUS_TIMER1_CC2(port, pin) SILABS_DBUS(port, pin, 67, 1, 2, 3) 71 #define SILABS_DBUS_TIMER1_CDTI0(port, pin) SILABS_DBUS(port, pin, 67, 1, 3, 4) 72 #define SILABS_DBUS_TIMER1_CDTI1(port, pin) SILABS_DBUS(port, pin, 67, 1, 4, 5) 73 #define SILABS_DBUS_TIMER1_CDTI2(port, pin) SILABS_DBUS(port, pin, 67, 1, 5, 6) 74 75 #define SILABS_DBUS_TIMER2_CC0(port, pin) SILABS_DBUS(port, pin, 75, 1, 0, 1) 76 #define SILABS_DBUS_TIMER2_CC1(port, pin) SILABS_DBUS(port, pin, 75, 1, 1, 2) 77 #define SILABS_DBUS_TIMER2_CC2(port, pin) SILABS_DBUS(port, pin, 75, 1, 2, 3) 78 #define SILABS_DBUS_TIMER2_CDTI0(port, pin) SILABS_DBUS(port, pin, 75, 1, 3, 4) 79 #define SILABS_DBUS_TIMER2_CDTI1(port, pin) SILABS_DBUS(port, pin, 75, 1, 4, 5) 80 #define SILABS_DBUS_TIMER2_CDTI2(port, pin) SILABS_DBUS(port, pin, 75, 1, 5, 6) 81 82 #define SILABS_DBUS_TIMER3_CC0(port, pin) SILABS_DBUS(port, pin, 83, 1, 0, 1) 83 #define SILABS_DBUS_TIMER3_CC1(port, pin) SILABS_DBUS(port, pin, 83, 1, 1, 2) 84 #define SILABS_DBUS_TIMER3_CC2(port, pin) SILABS_DBUS(port, pin, 83, 1, 2, 3) 85 #define SILABS_DBUS_TIMER3_CDTI0(port, pin) SILABS_DBUS(port, pin, 83, 1, 3, 4) 86 #define SILABS_DBUS_TIMER3_CDTI1(port, pin) SILABS_DBUS(port, pin, 83, 1, 4, 5) 87 #define SILABS_DBUS_TIMER3_CDTI2(port, pin) SILABS_DBUS(port, pin, 83, 1, 5, 6) 88 89 #define SILABS_DBUS_USART0_CS(port, pin) SILABS_DBUS(port, pin, 91, 1, 0, 1) 90 #define SILABS_DBUS_USART0_RTS(port, pin) SILABS_DBUS(port, pin, 91, 1, 1, 3) 91 #define SILABS_DBUS_USART0_RX(port, pin) SILABS_DBUS(port, pin, 91, 1, 2, 4) 92 #define SILABS_DBUS_USART0_CLK(port, pin) SILABS_DBUS(port, pin, 91, 1, 3, 5) 93 #define SILABS_DBUS_USART0_TX(port, pin) SILABS_DBUS(port, pin, 91, 1, 4, 6) 94 #define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 91, 0, 0, 2) 95 96 #define SILABS_DBUS_USART1_CS(port, pin) SILABS_DBUS(port, pin, 99, 1, 0, 1) 97 #define SILABS_DBUS_USART1_RTS(port, pin) SILABS_DBUS(port, pin, 99, 1, 1, 3) 98 #define SILABS_DBUS_USART1_RX(port, pin) SILABS_DBUS(port, pin, 99, 1, 2, 4) 99 #define SILABS_DBUS_USART1_CLK(port, pin) SILABS_DBUS(port, pin, 99, 1, 3, 5) 100 #define SILABS_DBUS_USART1_TX(port, pin) SILABS_DBUS(port, pin, 99, 1, 4, 6) 101 #define SILABS_DBUS_USART1_CTS(port, pin) SILABS_DBUS(port, pin, 99, 0, 0, 2) 102 103 #define SILABS_DBUS_USART2_CS(port, pin) SILABS_DBUS(port, pin, 107, 1, 0, 1) 104 #define SILABS_DBUS_USART2_RTS(port, pin) SILABS_DBUS(port, pin, 107, 1, 1, 3) 105 #define SILABS_DBUS_USART2_RX(port, pin) SILABS_DBUS(port, pin, 107, 1, 2, 4) 106 #define SILABS_DBUS_USART2_CLK(port, pin) SILABS_DBUS(port, pin, 107, 1, 3, 5) 107 #define SILABS_DBUS_USART2_TX(port, pin) SILABS_DBUS(port, pin, 107, 1, 4, 6) 108 #define SILABS_DBUS_USART2_CTS(port, pin) SILABS_DBUS(port, pin, 107, 0, 0, 2) 109 110 #define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0) 111 #define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1) 112 #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2) 113 #define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3) 114 #define ACMP0_ACMPOUT_PA4 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x4) 115 #define ACMP0_ACMPOUT_PA5 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x5) 116 #define ACMP0_ACMPOUT_PA6 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x6) 117 #define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0) 118 #define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1) 119 #define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0) 120 #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1) 121 #define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2) 122 #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3) 123 #define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4) 124 #define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5) 125 #define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0) 126 #define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1) 127 #define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2) 128 #define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3) 129 #define ACMP0_ACMPOUT_PD4 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x4) 130 131 #define ACMP1_ACMPOUT_PA0 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x0) 132 #define ACMP1_ACMPOUT_PA1 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x1) 133 #define ACMP1_ACMPOUT_PA2 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x2) 134 #define ACMP1_ACMPOUT_PA3 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x3) 135 #define ACMP1_ACMPOUT_PA4 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x4) 136 #define ACMP1_ACMPOUT_PA5 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x5) 137 #define ACMP1_ACMPOUT_PA6 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x6) 138 #define ACMP1_ACMPOUT_PB0 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x0) 139 #define ACMP1_ACMPOUT_PB1 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x1) 140 #define ACMP1_ACMPOUT_PC0 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x0) 141 #define ACMP1_ACMPOUT_PC1 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x1) 142 #define ACMP1_ACMPOUT_PC2 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x2) 143 #define ACMP1_ACMPOUT_PC3 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x3) 144 #define ACMP1_ACMPOUT_PC4 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x4) 145 #define ACMP1_ACMPOUT_PC5 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x5) 146 #define ACMP1_ACMPOUT_PD0 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x0) 147 #define ACMP1_ACMPOUT_PD1 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x1) 148 #define ACMP1_ACMPOUT_PD2 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x2) 149 #define ACMP1_ACMPOUT_PD3 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x3) 150 #define ACMP1_ACMPOUT_PD4 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x4) 151 152 #define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0) 153 #define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1) 154 #define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2) 155 #define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3) 156 #define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4) 157 #define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5) 158 #define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0) 159 #define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1) 160 #define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2) 161 #define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3) 162 #define CMU_CLKOUT0_PD4 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x4) 163 #define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0) 164 #define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1) 165 #define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2) 166 #define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3) 167 #define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4) 168 #define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5) 169 #define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0) 170 #define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1) 171 #define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2) 172 #define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3) 173 #define CMU_CLKOUT1_PD4 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x4) 174 #define CMU_CLKOUT2_PA0 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x0) 175 #define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1) 176 #define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2) 177 #define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3) 178 #define CMU_CLKOUT2_PA4 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x4) 179 #define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5) 180 #define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6) 181 #define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0) 182 #define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1) 183 #define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0) 184 #define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1) 185 #define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2) 186 #define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3) 187 #define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4) 188 #define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5) 189 #define CMU_CLKIN0_PD0 SILABS_DBUS_CMU_CLKIN0(0x3, 0x0) 190 #define CMU_CLKIN0_PD1 SILABS_DBUS_CMU_CLKIN0(0x3, 0x1) 191 #define CMU_CLKIN0_PD2 SILABS_DBUS_CMU_CLKIN0(0x3, 0x2) 192 #define CMU_CLKIN0_PD3 SILABS_DBUS_CMU_CLKIN0(0x3, 0x3) 193 #define CMU_CLKIN0_PD4 SILABS_DBUS_CMU_CLKIN0(0x3, 0x4) 194 195 #define PTI_DCLK_PC0 SILABS_DBUS_PTI_DCLK(0x2, 0x0) 196 #define PTI_DCLK_PC1 SILABS_DBUS_PTI_DCLK(0x2, 0x1) 197 #define PTI_DCLK_PC2 SILABS_DBUS_PTI_DCLK(0x2, 0x2) 198 #define PTI_DCLK_PC3 SILABS_DBUS_PTI_DCLK(0x2, 0x3) 199 #define PTI_DCLK_PC4 SILABS_DBUS_PTI_DCLK(0x2, 0x4) 200 #define PTI_DCLK_PC5 SILABS_DBUS_PTI_DCLK(0x2, 0x5) 201 #define PTI_DCLK_PD0 SILABS_DBUS_PTI_DCLK(0x3, 0x0) 202 #define PTI_DCLK_PD1 SILABS_DBUS_PTI_DCLK(0x3, 0x1) 203 #define PTI_DCLK_PD2 SILABS_DBUS_PTI_DCLK(0x3, 0x2) 204 #define PTI_DCLK_PD3 SILABS_DBUS_PTI_DCLK(0x3, 0x3) 205 #define PTI_DCLK_PD4 SILABS_DBUS_PTI_DCLK(0x3, 0x4) 206 #define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0) 207 #define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1) 208 #define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2) 209 #define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3) 210 #define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4) 211 #define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5) 212 #define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0) 213 #define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1) 214 #define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2) 215 #define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3) 216 #define PTI_DFRAME_PD4 SILABS_DBUS_PTI_DFRAME(0x3, 0x4) 217 #define PTI_DOUT_PC0 SILABS_DBUS_PTI_DOUT(0x2, 0x0) 218 #define PTI_DOUT_PC1 SILABS_DBUS_PTI_DOUT(0x2, 0x1) 219 #define PTI_DOUT_PC2 SILABS_DBUS_PTI_DOUT(0x2, 0x2) 220 #define PTI_DOUT_PC3 SILABS_DBUS_PTI_DOUT(0x2, 0x3) 221 #define PTI_DOUT_PC4 SILABS_DBUS_PTI_DOUT(0x2, 0x4) 222 #define PTI_DOUT_PC5 SILABS_DBUS_PTI_DOUT(0x2, 0x5) 223 #define PTI_DOUT_PD0 SILABS_DBUS_PTI_DOUT(0x3, 0x0) 224 #define PTI_DOUT_PD1 SILABS_DBUS_PTI_DOUT(0x3, 0x1) 225 #define PTI_DOUT_PD2 SILABS_DBUS_PTI_DOUT(0x3, 0x2) 226 #define PTI_DOUT_PD3 SILABS_DBUS_PTI_DOUT(0x3, 0x3) 227 #define PTI_DOUT_PD4 SILABS_DBUS_PTI_DOUT(0x3, 0x4) 228 229 #define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0) 230 #define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1) 231 #define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2) 232 #define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3) 233 #define I2C0_SCL_PA4 SILABS_DBUS_I2C0_SCL(0x0, 0x4) 234 #define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5) 235 #define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6) 236 #define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0) 237 #define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1) 238 #define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0) 239 #define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1) 240 #define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2) 241 #define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3) 242 #define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4) 243 #define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5) 244 #define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0) 245 #define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1) 246 #define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2) 247 #define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3) 248 #define I2C0_SCL_PD4 SILABS_DBUS_I2C0_SCL(0x3, 0x4) 249 #define I2C0_SDA_PA0 SILABS_DBUS_I2C0_SDA(0x0, 0x0) 250 #define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1) 251 #define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2) 252 #define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3) 253 #define I2C0_SDA_PA4 SILABS_DBUS_I2C0_SDA(0x0, 0x4) 254 #define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5) 255 #define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6) 256 #define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0) 257 #define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1) 258 #define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0) 259 #define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1) 260 #define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2) 261 #define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3) 262 #define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4) 263 #define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5) 264 #define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0) 265 #define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1) 266 #define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2) 267 #define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3) 268 #define I2C0_SDA_PD4 SILABS_DBUS_I2C0_SDA(0x3, 0x4) 269 270 #define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0) 271 #define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1) 272 #define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2) 273 #define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3) 274 #define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4) 275 #define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5) 276 #define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0) 277 #define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1) 278 #define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2) 279 #define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3) 280 #define I2C1_SCL_PD4 SILABS_DBUS_I2C1_SCL(0x3, 0x4) 281 #define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0) 282 #define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1) 283 #define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2) 284 #define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3) 285 #define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4) 286 #define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5) 287 #define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0) 288 #define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1) 289 #define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2) 290 #define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3) 291 #define I2C1_SDA_PD4 SILABS_DBUS_I2C1_SDA(0x3, 0x4) 292 293 #define LETIMER0_OUT0_PA0 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x0) 294 #define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1) 295 #define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2) 296 #define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3) 297 #define LETIMER0_OUT0_PA4 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x4) 298 #define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5) 299 #define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6) 300 #define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0) 301 #define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1) 302 #define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x0) 303 #define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1) 304 #define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2) 305 #define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3) 306 #define LETIMER0_OUT1_PA4 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x4) 307 #define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5) 308 #define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6) 309 #define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0) 310 #define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1) 311 312 #define MODEM_ANT0_PA0 SILABS_DBUS_MODEM_ANT0(0x0, 0x0) 313 #define MODEM_ANT0_PA1 SILABS_DBUS_MODEM_ANT0(0x0, 0x1) 314 #define MODEM_ANT0_PA2 SILABS_DBUS_MODEM_ANT0(0x0, 0x2) 315 #define MODEM_ANT0_PA3 SILABS_DBUS_MODEM_ANT0(0x0, 0x3) 316 #define MODEM_ANT0_PA4 SILABS_DBUS_MODEM_ANT0(0x0, 0x4) 317 #define MODEM_ANT0_PA5 SILABS_DBUS_MODEM_ANT0(0x0, 0x5) 318 #define MODEM_ANT0_PA6 SILABS_DBUS_MODEM_ANT0(0x0, 0x6) 319 #define MODEM_ANT0_PB0 SILABS_DBUS_MODEM_ANT0(0x1, 0x0) 320 #define MODEM_ANT0_PB1 SILABS_DBUS_MODEM_ANT0(0x1, 0x1) 321 #define MODEM_ANT0_PC0 SILABS_DBUS_MODEM_ANT0(0x2, 0x0) 322 #define MODEM_ANT0_PC1 SILABS_DBUS_MODEM_ANT0(0x2, 0x1) 323 #define MODEM_ANT0_PC2 SILABS_DBUS_MODEM_ANT0(0x2, 0x2) 324 #define MODEM_ANT0_PC3 SILABS_DBUS_MODEM_ANT0(0x2, 0x3) 325 #define MODEM_ANT0_PC4 SILABS_DBUS_MODEM_ANT0(0x2, 0x4) 326 #define MODEM_ANT0_PC5 SILABS_DBUS_MODEM_ANT0(0x2, 0x5) 327 #define MODEM_ANT0_PD0 SILABS_DBUS_MODEM_ANT0(0x3, 0x0) 328 #define MODEM_ANT0_PD1 SILABS_DBUS_MODEM_ANT0(0x3, 0x1) 329 #define MODEM_ANT0_PD2 SILABS_DBUS_MODEM_ANT0(0x3, 0x2) 330 #define MODEM_ANT0_PD3 SILABS_DBUS_MODEM_ANT0(0x3, 0x3) 331 #define MODEM_ANT0_PD4 SILABS_DBUS_MODEM_ANT0(0x3, 0x4) 332 #define MODEM_ANT1_PA0 SILABS_DBUS_MODEM_ANT1(0x0, 0x0) 333 #define MODEM_ANT1_PA1 SILABS_DBUS_MODEM_ANT1(0x0, 0x1) 334 #define MODEM_ANT1_PA2 SILABS_DBUS_MODEM_ANT1(0x0, 0x2) 335 #define MODEM_ANT1_PA3 SILABS_DBUS_MODEM_ANT1(0x0, 0x3) 336 #define MODEM_ANT1_PA4 SILABS_DBUS_MODEM_ANT1(0x0, 0x4) 337 #define MODEM_ANT1_PA5 SILABS_DBUS_MODEM_ANT1(0x0, 0x5) 338 #define MODEM_ANT1_PA6 SILABS_DBUS_MODEM_ANT1(0x0, 0x6) 339 #define MODEM_ANT1_PB0 SILABS_DBUS_MODEM_ANT1(0x1, 0x0) 340 #define MODEM_ANT1_PB1 SILABS_DBUS_MODEM_ANT1(0x1, 0x1) 341 #define MODEM_ANT1_PC0 SILABS_DBUS_MODEM_ANT1(0x2, 0x0) 342 #define MODEM_ANT1_PC1 SILABS_DBUS_MODEM_ANT1(0x2, 0x1) 343 #define MODEM_ANT1_PC2 SILABS_DBUS_MODEM_ANT1(0x2, 0x2) 344 #define MODEM_ANT1_PC3 SILABS_DBUS_MODEM_ANT1(0x2, 0x3) 345 #define MODEM_ANT1_PC4 SILABS_DBUS_MODEM_ANT1(0x2, 0x4) 346 #define MODEM_ANT1_PC5 SILABS_DBUS_MODEM_ANT1(0x2, 0x5) 347 #define MODEM_ANT1_PD0 SILABS_DBUS_MODEM_ANT1(0x3, 0x0) 348 #define MODEM_ANT1_PD1 SILABS_DBUS_MODEM_ANT1(0x3, 0x1) 349 #define MODEM_ANT1_PD2 SILABS_DBUS_MODEM_ANT1(0x3, 0x2) 350 #define MODEM_ANT1_PD3 SILABS_DBUS_MODEM_ANT1(0x3, 0x3) 351 #define MODEM_ANT1_PD4 SILABS_DBUS_MODEM_ANT1(0x3, 0x4) 352 #define MODEM_DCLK_PA0 SILABS_DBUS_MODEM_DCLK(0x0, 0x0) 353 #define MODEM_DCLK_PA1 SILABS_DBUS_MODEM_DCLK(0x0, 0x1) 354 #define MODEM_DCLK_PA2 SILABS_DBUS_MODEM_DCLK(0x0, 0x2) 355 #define MODEM_DCLK_PA3 SILABS_DBUS_MODEM_DCLK(0x0, 0x3) 356 #define MODEM_DCLK_PA4 SILABS_DBUS_MODEM_DCLK(0x0, 0x4) 357 #define MODEM_DCLK_PA5 SILABS_DBUS_MODEM_DCLK(0x0, 0x5) 358 #define MODEM_DCLK_PA6 SILABS_DBUS_MODEM_DCLK(0x0, 0x6) 359 #define MODEM_DCLK_PB0 SILABS_DBUS_MODEM_DCLK(0x1, 0x0) 360 #define MODEM_DCLK_PB1 SILABS_DBUS_MODEM_DCLK(0x1, 0x1) 361 #define MODEM_DOUT_PA0 SILABS_DBUS_MODEM_DOUT(0x0, 0x0) 362 #define MODEM_DOUT_PA1 SILABS_DBUS_MODEM_DOUT(0x0, 0x1) 363 #define MODEM_DOUT_PA2 SILABS_DBUS_MODEM_DOUT(0x0, 0x2) 364 #define MODEM_DOUT_PA3 SILABS_DBUS_MODEM_DOUT(0x0, 0x3) 365 #define MODEM_DOUT_PA4 SILABS_DBUS_MODEM_DOUT(0x0, 0x4) 366 #define MODEM_DOUT_PA5 SILABS_DBUS_MODEM_DOUT(0x0, 0x5) 367 #define MODEM_DOUT_PA6 SILABS_DBUS_MODEM_DOUT(0x0, 0x6) 368 #define MODEM_DOUT_PB0 SILABS_DBUS_MODEM_DOUT(0x1, 0x0) 369 #define MODEM_DOUT_PB1 SILABS_DBUS_MODEM_DOUT(0x1, 0x1) 370 #define MODEM_DIN_PA0 SILABS_DBUS_MODEM_DIN(0x0, 0x0) 371 #define MODEM_DIN_PA1 SILABS_DBUS_MODEM_DIN(0x0, 0x1) 372 #define MODEM_DIN_PA2 SILABS_DBUS_MODEM_DIN(0x0, 0x2) 373 #define MODEM_DIN_PA3 SILABS_DBUS_MODEM_DIN(0x0, 0x3) 374 #define MODEM_DIN_PA4 SILABS_DBUS_MODEM_DIN(0x0, 0x4) 375 #define MODEM_DIN_PA5 SILABS_DBUS_MODEM_DIN(0x0, 0x5) 376 #define MODEM_DIN_PA6 SILABS_DBUS_MODEM_DIN(0x0, 0x6) 377 #define MODEM_DIN_PB0 SILABS_DBUS_MODEM_DIN(0x1, 0x0) 378 #define MODEM_DIN_PB1 SILABS_DBUS_MODEM_DIN(0x1, 0x1) 379 380 #define PRS0_ASYNCH0_PA0 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x0) 381 #define PRS0_ASYNCH0_PA1 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1) 382 #define PRS0_ASYNCH0_PA2 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2) 383 #define PRS0_ASYNCH0_PA3 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3) 384 #define PRS0_ASYNCH0_PA4 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x4) 385 #define PRS0_ASYNCH0_PA5 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5) 386 #define PRS0_ASYNCH0_PA6 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6) 387 #define PRS0_ASYNCH0_PB0 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0) 388 #define PRS0_ASYNCH0_PB1 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1) 389 #define PRS0_ASYNCH1_PA0 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x0) 390 #define PRS0_ASYNCH1_PA1 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1) 391 #define PRS0_ASYNCH1_PA2 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2) 392 #define PRS0_ASYNCH1_PA3 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3) 393 #define PRS0_ASYNCH1_PA4 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x4) 394 #define PRS0_ASYNCH1_PA5 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5) 395 #define PRS0_ASYNCH1_PA6 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6) 396 #define PRS0_ASYNCH1_PB0 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0) 397 #define PRS0_ASYNCH1_PB1 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1) 398 #define PRS0_ASYNCH2_PA0 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x0) 399 #define PRS0_ASYNCH2_PA1 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1) 400 #define PRS0_ASYNCH2_PA2 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2) 401 #define PRS0_ASYNCH2_PA3 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3) 402 #define PRS0_ASYNCH2_PA4 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x4) 403 #define PRS0_ASYNCH2_PA5 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5) 404 #define PRS0_ASYNCH2_PA6 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6) 405 #define PRS0_ASYNCH2_PB0 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0) 406 #define PRS0_ASYNCH2_PB1 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1) 407 #define PRS0_ASYNCH3_PA0 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x0) 408 #define PRS0_ASYNCH3_PA1 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1) 409 #define PRS0_ASYNCH3_PA2 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2) 410 #define PRS0_ASYNCH3_PA3 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3) 411 #define PRS0_ASYNCH3_PA4 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x4) 412 #define PRS0_ASYNCH3_PA5 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5) 413 #define PRS0_ASYNCH3_PA6 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6) 414 #define PRS0_ASYNCH3_PB0 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0) 415 #define PRS0_ASYNCH3_PB1 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1) 416 #define PRS0_ASYNCH4_PA0 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x0) 417 #define PRS0_ASYNCH4_PA1 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1) 418 #define PRS0_ASYNCH4_PA2 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2) 419 #define PRS0_ASYNCH4_PA3 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3) 420 #define PRS0_ASYNCH4_PA4 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x4) 421 #define PRS0_ASYNCH4_PA5 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5) 422 #define PRS0_ASYNCH4_PA6 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6) 423 #define PRS0_ASYNCH4_PB0 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0) 424 #define PRS0_ASYNCH4_PB1 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1) 425 #define PRS0_ASYNCH5_PA0 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x0) 426 #define PRS0_ASYNCH5_PA1 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1) 427 #define PRS0_ASYNCH5_PA2 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2) 428 #define PRS0_ASYNCH5_PA3 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3) 429 #define PRS0_ASYNCH5_PA4 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x4) 430 #define PRS0_ASYNCH5_PA5 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5) 431 #define PRS0_ASYNCH5_PA6 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6) 432 #define PRS0_ASYNCH5_PB0 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0) 433 #define PRS0_ASYNCH5_PB1 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1) 434 #define PRS0_ASYNCH6_PC0 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0) 435 #define PRS0_ASYNCH6_PC1 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1) 436 #define PRS0_ASYNCH6_PC2 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2) 437 #define PRS0_ASYNCH6_PC3 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3) 438 #define PRS0_ASYNCH6_PC4 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4) 439 #define PRS0_ASYNCH6_PC5 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5) 440 #define PRS0_ASYNCH6_PD0 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0) 441 #define PRS0_ASYNCH6_PD1 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1) 442 #define PRS0_ASYNCH6_PD2 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2) 443 #define PRS0_ASYNCH6_PD3 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3) 444 #define PRS0_ASYNCH6_PD4 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x4) 445 #define PRS0_ASYNCH7_PC0 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0) 446 #define PRS0_ASYNCH7_PC1 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1) 447 #define PRS0_ASYNCH7_PC2 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2) 448 #define PRS0_ASYNCH7_PC3 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3) 449 #define PRS0_ASYNCH7_PC4 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4) 450 #define PRS0_ASYNCH7_PC5 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5) 451 #define PRS0_ASYNCH7_PD0 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0) 452 #define PRS0_ASYNCH7_PD1 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1) 453 #define PRS0_ASYNCH7_PD2 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2) 454 #define PRS0_ASYNCH7_PD3 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3) 455 #define PRS0_ASYNCH7_PD4 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x4) 456 #define PRS0_ASYNCH8_PC0 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0) 457 #define PRS0_ASYNCH8_PC1 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1) 458 #define PRS0_ASYNCH8_PC2 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2) 459 #define PRS0_ASYNCH8_PC3 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3) 460 #define PRS0_ASYNCH8_PC4 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4) 461 #define PRS0_ASYNCH8_PC5 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5) 462 #define PRS0_ASYNCH8_PD0 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0) 463 #define PRS0_ASYNCH8_PD1 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1) 464 #define PRS0_ASYNCH8_PD2 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2) 465 #define PRS0_ASYNCH8_PD3 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3) 466 #define PRS0_ASYNCH8_PD4 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x4) 467 #define PRS0_ASYNCH9_PC0 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0) 468 #define PRS0_ASYNCH9_PC1 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1) 469 #define PRS0_ASYNCH9_PC2 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2) 470 #define PRS0_ASYNCH9_PC3 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3) 471 #define PRS0_ASYNCH9_PC4 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4) 472 #define PRS0_ASYNCH9_PC5 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5) 473 #define PRS0_ASYNCH9_PD0 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0) 474 #define PRS0_ASYNCH9_PD1 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1) 475 #define PRS0_ASYNCH9_PD2 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2) 476 #define PRS0_ASYNCH9_PD3 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3) 477 #define PRS0_ASYNCH9_PD4 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x4) 478 #define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0) 479 #define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1) 480 #define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2) 481 #define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3) 482 #define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4) 483 #define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5) 484 #define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0) 485 #define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1) 486 #define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2) 487 #define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3) 488 #define PRS0_ASYNCH10_PD4 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x4) 489 #define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0) 490 #define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1) 491 #define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2) 492 #define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3) 493 #define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4) 494 #define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5) 495 #define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0) 496 #define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1) 497 #define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2) 498 #define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3) 499 #define PRS0_ASYNCH11_PD4 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x4) 500 #define PRS0_SYNCH0_PA0 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x0) 501 #define PRS0_SYNCH0_PA1 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1) 502 #define PRS0_SYNCH0_PA2 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2) 503 #define PRS0_SYNCH0_PA3 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3) 504 #define PRS0_SYNCH0_PA4 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x4) 505 #define PRS0_SYNCH0_PA5 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5) 506 #define PRS0_SYNCH0_PA6 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6) 507 #define PRS0_SYNCH0_PB0 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0) 508 #define PRS0_SYNCH0_PB1 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1) 509 #define PRS0_SYNCH0_PC0 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0) 510 #define PRS0_SYNCH0_PC1 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1) 511 #define PRS0_SYNCH0_PC2 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2) 512 #define PRS0_SYNCH0_PC3 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3) 513 #define PRS0_SYNCH0_PC4 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4) 514 #define PRS0_SYNCH0_PC5 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5) 515 #define PRS0_SYNCH0_PD0 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0) 516 #define PRS0_SYNCH0_PD1 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1) 517 #define PRS0_SYNCH0_PD2 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2) 518 #define PRS0_SYNCH0_PD3 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3) 519 #define PRS0_SYNCH0_PD4 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x4) 520 #define PRS0_SYNCH1_PA0 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x0) 521 #define PRS0_SYNCH1_PA1 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1) 522 #define PRS0_SYNCH1_PA2 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2) 523 #define PRS0_SYNCH1_PA3 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3) 524 #define PRS0_SYNCH1_PA4 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x4) 525 #define PRS0_SYNCH1_PA5 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5) 526 #define PRS0_SYNCH1_PA6 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6) 527 #define PRS0_SYNCH1_PB0 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0) 528 #define PRS0_SYNCH1_PB1 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1) 529 #define PRS0_SYNCH1_PC0 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0) 530 #define PRS0_SYNCH1_PC1 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1) 531 #define PRS0_SYNCH1_PC2 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2) 532 #define PRS0_SYNCH1_PC3 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3) 533 #define PRS0_SYNCH1_PC4 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4) 534 #define PRS0_SYNCH1_PC5 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5) 535 #define PRS0_SYNCH1_PD0 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0) 536 #define PRS0_SYNCH1_PD1 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1) 537 #define PRS0_SYNCH1_PD2 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2) 538 #define PRS0_SYNCH1_PD3 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3) 539 #define PRS0_SYNCH1_PD4 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x4) 540 #define PRS0_SYNCH2_PA0 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x0) 541 #define PRS0_SYNCH2_PA1 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1) 542 #define PRS0_SYNCH2_PA2 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2) 543 #define PRS0_SYNCH2_PA3 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3) 544 #define PRS0_SYNCH2_PA4 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x4) 545 #define PRS0_SYNCH2_PA5 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5) 546 #define PRS0_SYNCH2_PA6 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6) 547 #define PRS0_SYNCH2_PB0 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0) 548 #define PRS0_SYNCH2_PB1 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1) 549 #define PRS0_SYNCH2_PC0 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0) 550 #define PRS0_SYNCH2_PC1 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1) 551 #define PRS0_SYNCH2_PC2 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2) 552 #define PRS0_SYNCH2_PC3 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3) 553 #define PRS0_SYNCH2_PC4 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4) 554 #define PRS0_SYNCH2_PC5 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5) 555 #define PRS0_SYNCH2_PD0 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0) 556 #define PRS0_SYNCH2_PD1 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1) 557 #define PRS0_SYNCH2_PD2 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2) 558 #define PRS0_SYNCH2_PD3 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3) 559 #define PRS0_SYNCH2_PD4 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x4) 560 #define PRS0_SYNCH3_PA0 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x0) 561 #define PRS0_SYNCH3_PA1 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1) 562 #define PRS0_SYNCH3_PA2 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2) 563 #define PRS0_SYNCH3_PA3 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3) 564 #define PRS0_SYNCH3_PA4 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x4) 565 #define PRS0_SYNCH3_PA5 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5) 566 #define PRS0_SYNCH3_PA6 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6) 567 #define PRS0_SYNCH3_PB0 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0) 568 #define PRS0_SYNCH3_PB1 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1) 569 #define PRS0_SYNCH3_PC0 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0) 570 #define PRS0_SYNCH3_PC1 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1) 571 #define PRS0_SYNCH3_PC2 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2) 572 #define PRS0_SYNCH3_PC3 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3) 573 #define PRS0_SYNCH3_PC4 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4) 574 #define PRS0_SYNCH3_PC5 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5) 575 #define PRS0_SYNCH3_PD0 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0) 576 #define PRS0_SYNCH3_PD1 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1) 577 #define PRS0_SYNCH3_PD2 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2) 578 #define PRS0_SYNCH3_PD3 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3) 579 #define PRS0_SYNCH3_PD4 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x4) 580 581 #define TIMER0_CC0_PA0 SILABS_DBUS_TIMER0_CC0(0x0, 0x0) 582 #define TIMER0_CC0_PA1 SILABS_DBUS_TIMER0_CC0(0x0, 0x1) 583 #define TIMER0_CC0_PA2 SILABS_DBUS_TIMER0_CC0(0x0, 0x2) 584 #define TIMER0_CC0_PA3 SILABS_DBUS_TIMER0_CC0(0x0, 0x3) 585 #define TIMER0_CC0_PA4 SILABS_DBUS_TIMER0_CC0(0x0, 0x4) 586 #define TIMER0_CC0_PA5 SILABS_DBUS_TIMER0_CC0(0x0, 0x5) 587 #define TIMER0_CC0_PA6 SILABS_DBUS_TIMER0_CC0(0x0, 0x6) 588 #define TIMER0_CC0_PB0 SILABS_DBUS_TIMER0_CC0(0x1, 0x0) 589 #define TIMER0_CC0_PB1 SILABS_DBUS_TIMER0_CC0(0x1, 0x1) 590 #define TIMER0_CC0_PC0 SILABS_DBUS_TIMER0_CC0(0x2, 0x0) 591 #define TIMER0_CC0_PC1 SILABS_DBUS_TIMER0_CC0(0x2, 0x1) 592 #define TIMER0_CC0_PC2 SILABS_DBUS_TIMER0_CC0(0x2, 0x2) 593 #define TIMER0_CC0_PC3 SILABS_DBUS_TIMER0_CC0(0x2, 0x3) 594 #define TIMER0_CC0_PC4 SILABS_DBUS_TIMER0_CC0(0x2, 0x4) 595 #define TIMER0_CC0_PC5 SILABS_DBUS_TIMER0_CC0(0x2, 0x5) 596 #define TIMER0_CC0_PD0 SILABS_DBUS_TIMER0_CC0(0x3, 0x0) 597 #define TIMER0_CC0_PD1 SILABS_DBUS_TIMER0_CC0(0x3, 0x1) 598 #define TIMER0_CC0_PD2 SILABS_DBUS_TIMER0_CC0(0x3, 0x2) 599 #define TIMER0_CC0_PD3 SILABS_DBUS_TIMER0_CC0(0x3, 0x3) 600 #define TIMER0_CC0_PD4 SILABS_DBUS_TIMER0_CC0(0x3, 0x4) 601 #define TIMER0_CC1_PA0 SILABS_DBUS_TIMER0_CC1(0x0, 0x0) 602 #define TIMER0_CC1_PA1 SILABS_DBUS_TIMER0_CC1(0x0, 0x1) 603 #define TIMER0_CC1_PA2 SILABS_DBUS_TIMER0_CC1(0x0, 0x2) 604 #define TIMER0_CC1_PA3 SILABS_DBUS_TIMER0_CC1(0x0, 0x3) 605 #define TIMER0_CC1_PA4 SILABS_DBUS_TIMER0_CC1(0x0, 0x4) 606 #define TIMER0_CC1_PA5 SILABS_DBUS_TIMER0_CC1(0x0, 0x5) 607 #define TIMER0_CC1_PA6 SILABS_DBUS_TIMER0_CC1(0x0, 0x6) 608 #define TIMER0_CC1_PB0 SILABS_DBUS_TIMER0_CC1(0x1, 0x0) 609 #define TIMER0_CC1_PB1 SILABS_DBUS_TIMER0_CC1(0x1, 0x1) 610 #define TIMER0_CC1_PC0 SILABS_DBUS_TIMER0_CC1(0x2, 0x0) 611 #define TIMER0_CC1_PC1 SILABS_DBUS_TIMER0_CC1(0x2, 0x1) 612 #define TIMER0_CC1_PC2 SILABS_DBUS_TIMER0_CC1(0x2, 0x2) 613 #define TIMER0_CC1_PC3 SILABS_DBUS_TIMER0_CC1(0x2, 0x3) 614 #define TIMER0_CC1_PC4 SILABS_DBUS_TIMER0_CC1(0x2, 0x4) 615 #define TIMER0_CC1_PC5 SILABS_DBUS_TIMER0_CC1(0x2, 0x5) 616 #define TIMER0_CC1_PD0 SILABS_DBUS_TIMER0_CC1(0x3, 0x0) 617 #define TIMER0_CC1_PD1 SILABS_DBUS_TIMER0_CC1(0x3, 0x1) 618 #define TIMER0_CC1_PD2 SILABS_DBUS_TIMER0_CC1(0x3, 0x2) 619 #define TIMER0_CC1_PD3 SILABS_DBUS_TIMER0_CC1(0x3, 0x3) 620 #define TIMER0_CC1_PD4 SILABS_DBUS_TIMER0_CC1(0x3, 0x4) 621 #define TIMER0_CC2_PA0 SILABS_DBUS_TIMER0_CC2(0x0, 0x0) 622 #define TIMER0_CC2_PA1 SILABS_DBUS_TIMER0_CC2(0x0, 0x1) 623 #define TIMER0_CC2_PA2 SILABS_DBUS_TIMER0_CC2(0x0, 0x2) 624 #define TIMER0_CC2_PA3 SILABS_DBUS_TIMER0_CC2(0x0, 0x3) 625 #define TIMER0_CC2_PA4 SILABS_DBUS_TIMER0_CC2(0x0, 0x4) 626 #define TIMER0_CC2_PA5 SILABS_DBUS_TIMER0_CC2(0x0, 0x5) 627 #define TIMER0_CC2_PA6 SILABS_DBUS_TIMER0_CC2(0x0, 0x6) 628 #define TIMER0_CC2_PB0 SILABS_DBUS_TIMER0_CC2(0x1, 0x0) 629 #define TIMER0_CC2_PB1 SILABS_DBUS_TIMER0_CC2(0x1, 0x1) 630 #define TIMER0_CC2_PC0 SILABS_DBUS_TIMER0_CC2(0x2, 0x0) 631 #define TIMER0_CC2_PC1 SILABS_DBUS_TIMER0_CC2(0x2, 0x1) 632 #define TIMER0_CC2_PC2 SILABS_DBUS_TIMER0_CC2(0x2, 0x2) 633 #define TIMER0_CC2_PC3 SILABS_DBUS_TIMER0_CC2(0x2, 0x3) 634 #define TIMER0_CC2_PC4 SILABS_DBUS_TIMER0_CC2(0x2, 0x4) 635 #define TIMER0_CC2_PC5 SILABS_DBUS_TIMER0_CC2(0x2, 0x5) 636 #define TIMER0_CC2_PD0 SILABS_DBUS_TIMER0_CC2(0x3, 0x0) 637 #define TIMER0_CC2_PD1 SILABS_DBUS_TIMER0_CC2(0x3, 0x1) 638 #define TIMER0_CC2_PD2 SILABS_DBUS_TIMER0_CC2(0x3, 0x2) 639 #define TIMER0_CC2_PD3 SILABS_DBUS_TIMER0_CC2(0x3, 0x3) 640 #define TIMER0_CC2_PD4 SILABS_DBUS_TIMER0_CC2(0x3, 0x4) 641 #define TIMER0_CDTI0_PA0 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x0) 642 #define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1) 643 #define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2) 644 #define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3) 645 #define TIMER0_CDTI0_PA4 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x4) 646 #define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5) 647 #define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6) 648 #define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0) 649 #define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1) 650 #define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0) 651 #define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1) 652 #define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2) 653 #define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3) 654 #define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4) 655 #define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5) 656 #define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0) 657 #define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1) 658 #define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2) 659 #define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3) 660 #define TIMER0_CDTI0_PD4 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x4) 661 #define TIMER0_CDTI1_PA0 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x0) 662 #define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1) 663 #define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2) 664 #define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3) 665 #define TIMER0_CDTI1_PA4 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x4) 666 #define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5) 667 #define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6) 668 #define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0) 669 #define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1) 670 #define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0) 671 #define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1) 672 #define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2) 673 #define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3) 674 #define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4) 675 #define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5) 676 #define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0) 677 #define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1) 678 #define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2) 679 #define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3) 680 #define TIMER0_CDTI1_PD4 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x4) 681 #define TIMER0_CDTI2_PA0 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x0) 682 #define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1) 683 #define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2) 684 #define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3) 685 #define TIMER0_CDTI2_PA4 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x4) 686 #define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5) 687 #define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6) 688 #define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0) 689 #define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1) 690 #define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0) 691 #define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1) 692 #define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2) 693 #define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3) 694 #define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4) 695 #define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5) 696 #define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0) 697 #define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1) 698 #define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2) 699 #define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3) 700 #define TIMER0_CDTI2_PD4 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x4) 701 702 #define TIMER1_CC0_PA0 SILABS_DBUS_TIMER1_CC0(0x0, 0x0) 703 #define TIMER1_CC0_PA1 SILABS_DBUS_TIMER1_CC0(0x0, 0x1) 704 #define TIMER1_CC0_PA2 SILABS_DBUS_TIMER1_CC0(0x0, 0x2) 705 #define TIMER1_CC0_PA3 SILABS_DBUS_TIMER1_CC0(0x0, 0x3) 706 #define TIMER1_CC0_PA4 SILABS_DBUS_TIMER1_CC0(0x0, 0x4) 707 #define TIMER1_CC0_PA5 SILABS_DBUS_TIMER1_CC0(0x0, 0x5) 708 #define TIMER1_CC0_PA6 SILABS_DBUS_TIMER1_CC0(0x0, 0x6) 709 #define TIMER1_CC0_PB0 SILABS_DBUS_TIMER1_CC0(0x1, 0x0) 710 #define TIMER1_CC0_PB1 SILABS_DBUS_TIMER1_CC0(0x1, 0x1) 711 #define TIMER1_CC0_PC0 SILABS_DBUS_TIMER1_CC0(0x2, 0x0) 712 #define TIMER1_CC0_PC1 SILABS_DBUS_TIMER1_CC0(0x2, 0x1) 713 #define TIMER1_CC0_PC2 SILABS_DBUS_TIMER1_CC0(0x2, 0x2) 714 #define TIMER1_CC0_PC3 SILABS_DBUS_TIMER1_CC0(0x2, 0x3) 715 #define TIMER1_CC0_PC4 SILABS_DBUS_TIMER1_CC0(0x2, 0x4) 716 #define TIMER1_CC0_PC5 SILABS_DBUS_TIMER1_CC0(0x2, 0x5) 717 #define TIMER1_CC0_PD0 SILABS_DBUS_TIMER1_CC0(0x3, 0x0) 718 #define TIMER1_CC0_PD1 SILABS_DBUS_TIMER1_CC0(0x3, 0x1) 719 #define TIMER1_CC0_PD2 SILABS_DBUS_TIMER1_CC0(0x3, 0x2) 720 #define TIMER1_CC0_PD3 SILABS_DBUS_TIMER1_CC0(0x3, 0x3) 721 #define TIMER1_CC0_PD4 SILABS_DBUS_TIMER1_CC0(0x3, 0x4) 722 #define TIMER1_CC1_PA0 SILABS_DBUS_TIMER1_CC1(0x0, 0x0) 723 #define TIMER1_CC1_PA1 SILABS_DBUS_TIMER1_CC1(0x0, 0x1) 724 #define TIMER1_CC1_PA2 SILABS_DBUS_TIMER1_CC1(0x0, 0x2) 725 #define TIMER1_CC1_PA3 SILABS_DBUS_TIMER1_CC1(0x0, 0x3) 726 #define TIMER1_CC1_PA4 SILABS_DBUS_TIMER1_CC1(0x0, 0x4) 727 #define TIMER1_CC1_PA5 SILABS_DBUS_TIMER1_CC1(0x0, 0x5) 728 #define TIMER1_CC1_PA6 SILABS_DBUS_TIMER1_CC1(0x0, 0x6) 729 #define TIMER1_CC1_PB0 SILABS_DBUS_TIMER1_CC1(0x1, 0x0) 730 #define TIMER1_CC1_PB1 SILABS_DBUS_TIMER1_CC1(0x1, 0x1) 731 #define TIMER1_CC1_PC0 SILABS_DBUS_TIMER1_CC1(0x2, 0x0) 732 #define TIMER1_CC1_PC1 SILABS_DBUS_TIMER1_CC1(0x2, 0x1) 733 #define TIMER1_CC1_PC2 SILABS_DBUS_TIMER1_CC1(0x2, 0x2) 734 #define TIMER1_CC1_PC3 SILABS_DBUS_TIMER1_CC1(0x2, 0x3) 735 #define TIMER1_CC1_PC4 SILABS_DBUS_TIMER1_CC1(0x2, 0x4) 736 #define TIMER1_CC1_PC5 SILABS_DBUS_TIMER1_CC1(0x2, 0x5) 737 #define TIMER1_CC1_PD0 SILABS_DBUS_TIMER1_CC1(0x3, 0x0) 738 #define TIMER1_CC1_PD1 SILABS_DBUS_TIMER1_CC1(0x3, 0x1) 739 #define TIMER1_CC1_PD2 SILABS_DBUS_TIMER1_CC1(0x3, 0x2) 740 #define TIMER1_CC1_PD3 SILABS_DBUS_TIMER1_CC1(0x3, 0x3) 741 #define TIMER1_CC1_PD4 SILABS_DBUS_TIMER1_CC1(0x3, 0x4) 742 #define TIMER1_CC2_PA0 SILABS_DBUS_TIMER1_CC2(0x0, 0x0) 743 #define TIMER1_CC2_PA1 SILABS_DBUS_TIMER1_CC2(0x0, 0x1) 744 #define TIMER1_CC2_PA2 SILABS_DBUS_TIMER1_CC2(0x0, 0x2) 745 #define TIMER1_CC2_PA3 SILABS_DBUS_TIMER1_CC2(0x0, 0x3) 746 #define TIMER1_CC2_PA4 SILABS_DBUS_TIMER1_CC2(0x0, 0x4) 747 #define TIMER1_CC2_PA5 SILABS_DBUS_TIMER1_CC2(0x0, 0x5) 748 #define TIMER1_CC2_PA6 SILABS_DBUS_TIMER1_CC2(0x0, 0x6) 749 #define TIMER1_CC2_PB0 SILABS_DBUS_TIMER1_CC2(0x1, 0x0) 750 #define TIMER1_CC2_PB1 SILABS_DBUS_TIMER1_CC2(0x1, 0x1) 751 #define TIMER1_CC2_PC0 SILABS_DBUS_TIMER1_CC2(0x2, 0x0) 752 #define TIMER1_CC2_PC1 SILABS_DBUS_TIMER1_CC2(0x2, 0x1) 753 #define TIMER1_CC2_PC2 SILABS_DBUS_TIMER1_CC2(0x2, 0x2) 754 #define TIMER1_CC2_PC3 SILABS_DBUS_TIMER1_CC2(0x2, 0x3) 755 #define TIMER1_CC2_PC4 SILABS_DBUS_TIMER1_CC2(0x2, 0x4) 756 #define TIMER1_CC2_PC5 SILABS_DBUS_TIMER1_CC2(0x2, 0x5) 757 #define TIMER1_CC2_PD0 SILABS_DBUS_TIMER1_CC2(0x3, 0x0) 758 #define TIMER1_CC2_PD1 SILABS_DBUS_TIMER1_CC2(0x3, 0x1) 759 #define TIMER1_CC2_PD2 SILABS_DBUS_TIMER1_CC2(0x3, 0x2) 760 #define TIMER1_CC2_PD3 SILABS_DBUS_TIMER1_CC2(0x3, 0x3) 761 #define TIMER1_CC2_PD4 SILABS_DBUS_TIMER1_CC2(0x3, 0x4) 762 #define TIMER1_CDTI0_PA0 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x0) 763 #define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1) 764 #define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2) 765 #define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3) 766 #define TIMER1_CDTI0_PA4 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x4) 767 #define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5) 768 #define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6) 769 #define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0) 770 #define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1) 771 #define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0) 772 #define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1) 773 #define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2) 774 #define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3) 775 #define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4) 776 #define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5) 777 #define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0) 778 #define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1) 779 #define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2) 780 #define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3) 781 #define TIMER1_CDTI0_PD4 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x4) 782 #define TIMER1_CDTI1_PA0 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x0) 783 #define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1) 784 #define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2) 785 #define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3) 786 #define TIMER1_CDTI1_PA4 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x4) 787 #define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5) 788 #define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6) 789 #define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0) 790 #define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1) 791 #define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0) 792 #define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1) 793 #define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2) 794 #define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3) 795 #define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4) 796 #define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5) 797 #define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0) 798 #define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1) 799 #define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2) 800 #define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3) 801 #define TIMER1_CDTI1_PD4 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x4) 802 #define TIMER1_CDTI2_PA0 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x0) 803 #define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1) 804 #define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2) 805 #define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3) 806 #define TIMER1_CDTI2_PA4 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x4) 807 #define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5) 808 #define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6) 809 #define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0) 810 #define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1) 811 #define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0) 812 #define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1) 813 #define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2) 814 #define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3) 815 #define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4) 816 #define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5) 817 #define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0) 818 #define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1) 819 #define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2) 820 #define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3) 821 #define TIMER1_CDTI2_PD4 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x4) 822 823 #define TIMER2_CC0_PA0 SILABS_DBUS_TIMER2_CC0(0x0, 0x0) 824 #define TIMER2_CC0_PA1 SILABS_DBUS_TIMER2_CC0(0x0, 0x1) 825 #define TIMER2_CC0_PA2 SILABS_DBUS_TIMER2_CC0(0x0, 0x2) 826 #define TIMER2_CC0_PA3 SILABS_DBUS_TIMER2_CC0(0x0, 0x3) 827 #define TIMER2_CC0_PA4 SILABS_DBUS_TIMER2_CC0(0x0, 0x4) 828 #define TIMER2_CC0_PA5 SILABS_DBUS_TIMER2_CC0(0x0, 0x5) 829 #define TIMER2_CC0_PA6 SILABS_DBUS_TIMER2_CC0(0x0, 0x6) 830 #define TIMER2_CC0_PB0 SILABS_DBUS_TIMER2_CC0(0x1, 0x0) 831 #define TIMER2_CC0_PB1 SILABS_DBUS_TIMER2_CC0(0x1, 0x1) 832 #define TIMER2_CC1_PA0 SILABS_DBUS_TIMER2_CC1(0x0, 0x0) 833 #define TIMER2_CC1_PA1 SILABS_DBUS_TIMER2_CC1(0x0, 0x1) 834 #define TIMER2_CC1_PA2 SILABS_DBUS_TIMER2_CC1(0x0, 0x2) 835 #define TIMER2_CC1_PA3 SILABS_DBUS_TIMER2_CC1(0x0, 0x3) 836 #define TIMER2_CC1_PA4 SILABS_DBUS_TIMER2_CC1(0x0, 0x4) 837 #define TIMER2_CC1_PA5 SILABS_DBUS_TIMER2_CC1(0x0, 0x5) 838 #define TIMER2_CC1_PA6 SILABS_DBUS_TIMER2_CC1(0x0, 0x6) 839 #define TIMER2_CC1_PB0 SILABS_DBUS_TIMER2_CC1(0x1, 0x0) 840 #define TIMER2_CC1_PB1 SILABS_DBUS_TIMER2_CC1(0x1, 0x1) 841 #define TIMER2_CC2_PA0 SILABS_DBUS_TIMER2_CC2(0x0, 0x0) 842 #define TIMER2_CC2_PA1 SILABS_DBUS_TIMER2_CC2(0x0, 0x1) 843 #define TIMER2_CC2_PA2 SILABS_DBUS_TIMER2_CC2(0x0, 0x2) 844 #define TIMER2_CC2_PA3 SILABS_DBUS_TIMER2_CC2(0x0, 0x3) 845 #define TIMER2_CC2_PA4 SILABS_DBUS_TIMER2_CC2(0x0, 0x4) 846 #define TIMER2_CC2_PA5 SILABS_DBUS_TIMER2_CC2(0x0, 0x5) 847 #define TIMER2_CC2_PA6 SILABS_DBUS_TIMER2_CC2(0x0, 0x6) 848 #define TIMER2_CC2_PB0 SILABS_DBUS_TIMER2_CC2(0x1, 0x0) 849 #define TIMER2_CC2_PB1 SILABS_DBUS_TIMER2_CC2(0x1, 0x1) 850 #define TIMER2_CDTI0_PA0 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x0) 851 #define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1) 852 #define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2) 853 #define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3) 854 #define TIMER2_CDTI0_PA4 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x4) 855 #define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5) 856 #define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6) 857 #define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0) 858 #define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1) 859 #define TIMER2_CDTI1_PA0 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x0) 860 #define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1) 861 #define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2) 862 #define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3) 863 #define TIMER2_CDTI1_PA4 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x4) 864 #define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5) 865 #define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6) 866 #define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0) 867 #define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1) 868 #define TIMER2_CDTI2_PA0 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x0) 869 #define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1) 870 #define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2) 871 #define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3) 872 #define TIMER2_CDTI2_PA4 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x4) 873 #define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5) 874 #define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6) 875 #define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0) 876 #define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1) 877 878 #define TIMER3_CC0_PC0 SILABS_DBUS_TIMER3_CC0(0x2, 0x0) 879 #define TIMER3_CC0_PC1 SILABS_DBUS_TIMER3_CC0(0x2, 0x1) 880 #define TIMER3_CC0_PC2 SILABS_DBUS_TIMER3_CC0(0x2, 0x2) 881 #define TIMER3_CC0_PC3 SILABS_DBUS_TIMER3_CC0(0x2, 0x3) 882 #define TIMER3_CC0_PC4 SILABS_DBUS_TIMER3_CC0(0x2, 0x4) 883 #define TIMER3_CC0_PC5 SILABS_DBUS_TIMER3_CC0(0x2, 0x5) 884 #define TIMER3_CC0_PD0 SILABS_DBUS_TIMER3_CC0(0x3, 0x0) 885 #define TIMER3_CC0_PD1 SILABS_DBUS_TIMER3_CC0(0x3, 0x1) 886 #define TIMER3_CC0_PD2 SILABS_DBUS_TIMER3_CC0(0x3, 0x2) 887 #define TIMER3_CC0_PD3 SILABS_DBUS_TIMER3_CC0(0x3, 0x3) 888 #define TIMER3_CC0_PD4 SILABS_DBUS_TIMER3_CC0(0x3, 0x4) 889 #define TIMER3_CC1_PC0 SILABS_DBUS_TIMER3_CC1(0x2, 0x0) 890 #define TIMER3_CC1_PC1 SILABS_DBUS_TIMER3_CC1(0x2, 0x1) 891 #define TIMER3_CC1_PC2 SILABS_DBUS_TIMER3_CC1(0x2, 0x2) 892 #define TIMER3_CC1_PC3 SILABS_DBUS_TIMER3_CC1(0x2, 0x3) 893 #define TIMER3_CC1_PC4 SILABS_DBUS_TIMER3_CC1(0x2, 0x4) 894 #define TIMER3_CC1_PC5 SILABS_DBUS_TIMER3_CC1(0x2, 0x5) 895 #define TIMER3_CC1_PD0 SILABS_DBUS_TIMER3_CC1(0x3, 0x0) 896 #define TIMER3_CC1_PD1 SILABS_DBUS_TIMER3_CC1(0x3, 0x1) 897 #define TIMER3_CC1_PD2 SILABS_DBUS_TIMER3_CC1(0x3, 0x2) 898 #define TIMER3_CC1_PD3 SILABS_DBUS_TIMER3_CC1(0x3, 0x3) 899 #define TIMER3_CC1_PD4 SILABS_DBUS_TIMER3_CC1(0x3, 0x4) 900 #define TIMER3_CC2_PC0 SILABS_DBUS_TIMER3_CC2(0x2, 0x0) 901 #define TIMER3_CC2_PC1 SILABS_DBUS_TIMER3_CC2(0x2, 0x1) 902 #define TIMER3_CC2_PC2 SILABS_DBUS_TIMER3_CC2(0x2, 0x2) 903 #define TIMER3_CC2_PC3 SILABS_DBUS_TIMER3_CC2(0x2, 0x3) 904 #define TIMER3_CC2_PC4 SILABS_DBUS_TIMER3_CC2(0x2, 0x4) 905 #define TIMER3_CC2_PC5 SILABS_DBUS_TIMER3_CC2(0x2, 0x5) 906 #define TIMER3_CC2_PD0 SILABS_DBUS_TIMER3_CC2(0x3, 0x0) 907 #define TIMER3_CC2_PD1 SILABS_DBUS_TIMER3_CC2(0x3, 0x1) 908 #define TIMER3_CC2_PD2 SILABS_DBUS_TIMER3_CC2(0x3, 0x2) 909 #define TIMER3_CC2_PD3 SILABS_DBUS_TIMER3_CC2(0x3, 0x3) 910 #define TIMER3_CC2_PD4 SILABS_DBUS_TIMER3_CC2(0x3, 0x4) 911 #define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0) 912 #define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1) 913 #define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2) 914 #define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3) 915 #define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4) 916 #define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5) 917 #define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0) 918 #define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1) 919 #define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2) 920 #define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3) 921 #define TIMER3_CDTI0_PD4 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x4) 922 #define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0) 923 #define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1) 924 #define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2) 925 #define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3) 926 #define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4) 927 #define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5) 928 #define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0) 929 #define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1) 930 #define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2) 931 #define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3) 932 #define TIMER3_CDTI1_PD4 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x4) 933 #define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0) 934 #define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1) 935 #define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2) 936 #define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3) 937 #define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4) 938 #define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5) 939 #define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0) 940 #define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1) 941 #define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2) 942 #define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3) 943 #define TIMER3_CDTI2_PD4 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x4) 944 945 #define USART0_CS_PA0 SILABS_DBUS_USART0_CS(0x0, 0x0) 946 #define USART0_CS_PA1 SILABS_DBUS_USART0_CS(0x0, 0x1) 947 #define USART0_CS_PA2 SILABS_DBUS_USART0_CS(0x0, 0x2) 948 #define USART0_CS_PA3 SILABS_DBUS_USART0_CS(0x0, 0x3) 949 #define USART0_CS_PA4 SILABS_DBUS_USART0_CS(0x0, 0x4) 950 #define USART0_CS_PA5 SILABS_DBUS_USART0_CS(0x0, 0x5) 951 #define USART0_CS_PA6 SILABS_DBUS_USART0_CS(0x0, 0x6) 952 #define USART0_CS_PB0 SILABS_DBUS_USART0_CS(0x1, 0x0) 953 #define USART0_CS_PB1 SILABS_DBUS_USART0_CS(0x1, 0x1) 954 #define USART0_CS_PC0 SILABS_DBUS_USART0_CS(0x2, 0x0) 955 #define USART0_CS_PC1 SILABS_DBUS_USART0_CS(0x2, 0x1) 956 #define USART0_CS_PC2 SILABS_DBUS_USART0_CS(0x2, 0x2) 957 #define USART0_CS_PC3 SILABS_DBUS_USART0_CS(0x2, 0x3) 958 #define USART0_CS_PC4 SILABS_DBUS_USART0_CS(0x2, 0x4) 959 #define USART0_CS_PC5 SILABS_DBUS_USART0_CS(0x2, 0x5) 960 #define USART0_CS_PD0 SILABS_DBUS_USART0_CS(0x3, 0x0) 961 #define USART0_CS_PD1 SILABS_DBUS_USART0_CS(0x3, 0x1) 962 #define USART0_CS_PD2 SILABS_DBUS_USART0_CS(0x3, 0x2) 963 #define USART0_CS_PD3 SILABS_DBUS_USART0_CS(0x3, 0x3) 964 #define USART0_CS_PD4 SILABS_DBUS_USART0_CS(0x3, 0x4) 965 #define USART0_RTS_PA0 SILABS_DBUS_USART0_RTS(0x0, 0x0) 966 #define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1) 967 #define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2) 968 #define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3) 969 #define USART0_RTS_PA4 SILABS_DBUS_USART0_RTS(0x0, 0x4) 970 #define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5) 971 #define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6) 972 #define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0) 973 #define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1) 974 #define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0) 975 #define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1) 976 #define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2) 977 #define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3) 978 #define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4) 979 #define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5) 980 #define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0) 981 #define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1) 982 #define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2) 983 #define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3) 984 #define USART0_RTS_PD4 SILABS_DBUS_USART0_RTS(0x3, 0x4) 985 #define USART0_RX_PA0 SILABS_DBUS_USART0_RX(0x0, 0x0) 986 #define USART0_RX_PA1 SILABS_DBUS_USART0_RX(0x0, 0x1) 987 #define USART0_RX_PA2 SILABS_DBUS_USART0_RX(0x0, 0x2) 988 #define USART0_RX_PA3 SILABS_DBUS_USART0_RX(0x0, 0x3) 989 #define USART0_RX_PA4 SILABS_DBUS_USART0_RX(0x0, 0x4) 990 #define USART0_RX_PA5 SILABS_DBUS_USART0_RX(0x0, 0x5) 991 #define USART0_RX_PA6 SILABS_DBUS_USART0_RX(0x0, 0x6) 992 #define USART0_RX_PB0 SILABS_DBUS_USART0_RX(0x1, 0x0) 993 #define USART0_RX_PB1 SILABS_DBUS_USART0_RX(0x1, 0x1) 994 #define USART0_RX_PC0 SILABS_DBUS_USART0_RX(0x2, 0x0) 995 #define USART0_RX_PC1 SILABS_DBUS_USART0_RX(0x2, 0x1) 996 #define USART0_RX_PC2 SILABS_DBUS_USART0_RX(0x2, 0x2) 997 #define USART0_RX_PC3 SILABS_DBUS_USART0_RX(0x2, 0x3) 998 #define USART0_RX_PC4 SILABS_DBUS_USART0_RX(0x2, 0x4) 999 #define USART0_RX_PC5 SILABS_DBUS_USART0_RX(0x2, 0x5) 1000 #define USART0_RX_PD0 SILABS_DBUS_USART0_RX(0x3, 0x0) 1001 #define USART0_RX_PD1 SILABS_DBUS_USART0_RX(0x3, 0x1) 1002 #define USART0_RX_PD2 SILABS_DBUS_USART0_RX(0x3, 0x2) 1003 #define USART0_RX_PD3 SILABS_DBUS_USART0_RX(0x3, 0x3) 1004 #define USART0_RX_PD4 SILABS_DBUS_USART0_RX(0x3, 0x4) 1005 #define USART0_CLK_PA0 SILABS_DBUS_USART0_CLK(0x0, 0x0) 1006 #define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1) 1007 #define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2) 1008 #define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3) 1009 #define USART0_CLK_PA4 SILABS_DBUS_USART0_CLK(0x0, 0x4) 1010 #define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5) 1011 #define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6) 1012 #define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0) 1013 #define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1) 1014 #define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0) 1015 #define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1) 1016 #define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2) 1017 #define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3) 1018 #define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4) 1019 #define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5) 1020 #define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0) 1021 #define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1) 1022 #define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2) 1023 #define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3) 1024 #define USART0_CLK_PD4 SILABS_DBUS_USART0_CLK(0x3, 0x4) 1025 #define USART0_TX_PA0 SILABS_DBUS_USART0_TX(0x0, 0x0) 1026 #define USART0_TX_PA1 SILABS_DBUS_USART0_TX(0x0, 0x1) 1027 #define USART0_TX_PA2 SILABS_DBUS_USART0_TX(0x0, 0x2) 1028 #define USART0_TX_PA3 SILABS_DBUS_USART0_TX(0x0, 0x3) 1029 #define USART0_TX_PA4 SILABS_DBUS_USART0_TX(0x0, 0x4) 1030 #define USART0_TX_PA5 SILABS_DBUS_USART0_TX(0x0, 0x5) 1031 #define USART0_TX_PA6 SILABS_DBUS_USART0_TX(0x0, 0x6) 1032 #define USART0_TX_PB0 SILABS_DBUS_USART0_TX(0x1, 0x0) 1033 #define USART0_TX_PB1 SILABS_DBUS_USART0_TX(0x1, 0x1) 1034 #define USART0_TX_PC0 SILABS_DBUS_USART0_TX(0x2, 0x0) 1035 #define USART0_TX_PC1 SILABS_DBUS_USART0_TX(0x2, 0x1) 1036 #define USART0_TX_PC2 SILABS_DBUS_USART0_TX(0x2, 0x2) 1037 #define USART0_TX_PC3 SILABS_DBUS_USART0_TX(0x2, 0x3) 1038 #define USART0_TX_PC4 SILABS_DBUS_USART0_TX(0x2, 0x4) 1039 #define USART0_TX_PC5 SILABS_DBUS_USART0_TX(0x2, 0x5) 1040 #define USART0_TX_PD0 SILABS_DBUS_USART0_TX(0x3, 0x0) 1041 #define USART0_TX_PD1 SILABS_DBUS_USART0_TX(0x3, 0x1) 1042 #define USART0_TX_PD2 SILABS_DBUS_USART0_TX(0x3, 0x2) 1043 #define USART0_TX_PD3 SILABS_DBUS_USART0_TX(0x3, 0x3) 1044 #define USART0_TX_PD4 SILABS_DBUS_USART0_TX(0x3, 0x4) 1045 #define USART0_CTS_PA0 SILABS_DBUS_USART0_CTS(0x0, 0x0) 1046 #define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1) 1047 #define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2) 1048 #define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3) 1049 #define USART0_CTS_PA4 SILABS_DBUS_USART0_CTS(0x0, 0x4) 1050 #define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5) 1051 #define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6) 1052 #define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0) 1053 #define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1) 1054 #define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0) 1055 #define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1) 1056 #define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2) 1057 #define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3) 1058 #define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4) 1059 #define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5) 1060 #define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0) 1061 #define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1) 1062 #define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2) 1063 #define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3) 1064 #define USART0_CTS_PD4 SILABS_DBUS_USART0_CTS(0x3, 0x4) 1065 1066 #define USART1_CS_PA0 SILABS_DBUS_USART1_CS(0x0, 0x0) 1067 #define USART1_CS_PA1 SILABS_DBUS_USART1_CS(0x0, 0x1) 1068 #define USART1_CS_PA2 SILABS_DBUS_USART1_CS(0x0, 0x2) 1069 #define USART1_CS_PA3 SILABS_DBUS_USART1_CS(0x0, 0x3) 1070 #define USART1_CS_PA4 SILABS_DBUS_USART1_CS(0x0, 0x4) 1071 #define USART1_CS_PA5 SILABS_DBUS_USART1_CS(0x0, 0x5) 1072 #define USART1_CS_PA6 SILABS_DBUS_USART1_CS(0x0, 0x6) 1073 #define USART1_CS_PB0 SILABS_DBUS_USART1_CS(0x1, 0x0) 1074 #define USART1_CS_PB1 SILABS_DBUS_USART1_CS(0x1, 0x1) 1075 #define USART1_RTS_PA0 SILABS_DBUS_USART1_RTS(0x0, 0x0) 1076 #define USART1_RTS_PA1 SILABS_DBUS_USART1_RTS(0x0, 0x1) 1077 #define USART1_RTS_PA2 SILABS_DBUS_USART1_RTS(0x0, 0x2) 1078 #define USART1_RTS_PA3 SILABS_DBUS_USART1_RTS(0x0, 0x3) 1079 #define USART1_RTS_PA4 SILABS_DBUS_USART1_RTS(0x0, 0x4) 1080 #define USART1_RTS_PA5 SILABS_DBUS_USART1_RTS(0x0, 0x5) 1081 #define USART1_RTS_PA6 SILABS_DBUS_USART1_RTS(0x0, 0x6) 1082 #define USART1_RTS_PB0 SILABS_DBUS_USART1_RTS(0x1, 0x0) 1083 #define USART1_RTS_PB1 SILABS_DBUS_USART1_RTS(0x1, 0x1) 1084 #define USART1_RX_PA0 SILABS_DBUS_USART1_RX(0x0, 0x0) 1085 #define USART1_RX_PA1 SILABS_DBUS_USART1_RX(0x0, 0x1) 1086 #define USART1_RX_PA2 SILABS_DBUS_USART1_RX(0x0, 0x2) 1087 #define USART1_RX_PA3 SILABS_DBUS_USART1_RX(0x0, 0x3) 1088 #define USART1_RX_PA4 SILABS_DBUS_USART1_RX(0x0, 0x4) 1089 #define USART1_RX_PA5 SILABS_DBUS_USART1_RX(0x0, 0x5) 1090 #define USART1_RX_PA6 SILABS_DBUS_USART1_RX(0x0, 0x6) 1091 #define USART1_RX_PB0 SILABS_DBUS_USART1_RX(0x1, 0x0) 1092 #define USART1_RX_PB1 SILABS_DBUS_USART1_RX(0x1, 0x1) 1093 #define USART1_CLK_PA0 SILABS_DBUS_USART1_CLK(0x0, 0x0) 1094 #define USART1_CLK_PA1 SILABS_DBUS_USART1_CLK(0x0, 0x1) 1095 #define USART1_CLK_PA2 SILABS_DBUS_USART1_CLK(0x0, 0x2) 1096 #define USART1_CLK_PA3 SILABS_DBUS_USART1_CLK(0x0, 0x3) 1097 #define USART1_CLK_PA4 SILABS_DBUS_USART1_CLK(0x0, 0x4) 1098 #define USART1_CLK_PA5 SILABS_DBUS_USART1_CLK(0x0, 0x5) 1099 #define USART1_CLK_PA6 SILABS_DBUS_USART1_CLK(0x0, 0x6) 1100 #define USART1_CLK_PB0 SILABS_DBUS_USART1_CLK(0x1, 0x0) 1101 #define USART1_CLK_PB1 SILABS_DBUS_USART1_CLK(0x1, 0x1) 1102 #define USART1_TX_PA0 SILABS_DBUS_USART1_TX(0x0, 0x0) 1103 #define USART1_TX_PA1 SILABS_DBUS_USART1_TX(0x0, 0x1) 1104 #define USART1_TX_PA2 SILABS_DBUS_USART1_TX(0x0, 0x2) 1105 #define USART1_TX_PA3 SILABS_DBUS_USART1_TX(0x0, 0x3) 1106 #define USART1_TX_PA4 SILABS_DBUS_USART1_TX(0x0, 0x4) 1107 #define USART1_TX_PA5 SILABS_DBUS_USART1_TX(0x0, 0x5) 1108 #define USART1_TX_PA6 SILABS_DBUS_USART1_TX(0x0, 0x6) 1109 #define USART1_TX_PB0 SILABS_DBUS_USART1_TX(0x1, 0x0) 1110 #define USART1_TX_PB1 SILABS_DBUS_USART1_TX(0x1, 0x1) 1111 #define USART1_CTS_PA0 SILABS_DBUS_USART1_CTS(0x0, 0x0) 1112 #define USART1_CTS_PA1 SILABS_DBUS_USART1_CTS(0x0, 0x1) 1113 #define USART1_CTS_PA2 SILABS_DBUS_USART1_CTS(0x0, 0x2) 1114 #define USART1_CTS_PA3 SILABS_DBUS_USART1_CTS(0x0, 0x3) 1115 #define USART1_CTS_PA4 SILABS_DBUS_USART1_CTS(0x0, 0x4) 1116 #define USART1_CTS_PA5 SILABS_DBUS_USART1_CTS(0x0, 0x5) 1117 #define USART1_CTS_PA6 SILABS_DBUS_USART1_CTS(0x0, 0x6) 1118 #define USART1_CTS_PB0 SILABS_DBUS_USART1_CTS(0x1, 0x0) 1119 #define USART1_CTS_PB1 SILABS_DBUS_USART1_CTS(0x1, 0x1) 1120 1121 #define USART2_CS_PC0 SILABS_DBUS_USART2_CS(0x2, 0x0) 1122 #define USART2_CS_PC1 SILABS_DBUS_USART2_CS(0x2, 0x1) 1123 #define USART2_CS_PC2 SILABS_DBUS_USART2_CS(0x2, 0x2) 1124 #define USART2_CS_PC3 SILABS_DBUS_USART2_CS(0x2, 0x3) 1125 #define USART2_CS_PC4 SILABS_DBUS_USART2_CS(0x2, 0x4) 1126 #define USART2_CS_PC5 SILABS_DBUS_USART2_CS(0x2, 0x5) 1127 #define USART2_CS_PD0 SILABS_DBUS_USART2_CS(0x3, 0x0) 1128 #define USART2_CS_PD1 SILABS_DBUS_USART2_CS(0x3, 0x1) 1129 #define USART2_CS_PD2 SILABS_DBUS_USART2_CS(0x3, 0x2) 1130 #define USART2_CS_PD3 SILABS_DBUS_USART2_CS(0x3, 0x3) 1131 #define USART2_CS_PD4 SILABS_DBUS_USART2_CS(0x3, 0x4) 1132 #define USART2_RTS_PC0 SILABS_DBUS_USART2_RTS(0x2, 0x0) 1133 #define USART2_RTS_PC1 SILABS_DBUS_USART2_RTS(0x2, 0x1) 1134 #define USART2_RTS_PC2 SILABS_DBUS_USART2_RTS(0x2, 0x2) 1135 #define USART2_RTS_PC3 SILABS_DBUS_USART2_RTS(0x2, 0x3) 1136 #define USART2_RTS_PC4 SILABS_DBUS_USART2_RTS(0x2, 0x4) 1137 #define USART2_RTS_PC5 SILABS_DBUS_USART2_RTS(0x2, 0x5) 1138 #define USART2_RTS_PD0 SILABS_DBUS_USART2_RTS(0x3, 0x0) 1139 #define USART2_RTS_PD1 SILABS_DBUS_USART2_RTS(0x3, 0x1) 1140 #define USART2_RTS_PD2 SILABS_DBUS_USART2_RTS(0x3, 0x2) 1141 #define USART2_RTS_PD3 SILABS_DBUS_USART2_RTS(0x3, 0x3) 1142 #define USART2_RTS_PD4 SILABS_DBUS_USART2_RTS(0x3, 0x4) 1143 #define USART2_RX_PC0 SILABS_DBUS_USART2_RX(0x2, 0x0) 1144 #define USART2_RX_PC1 SILABS_DBUS_USART2_RX(0x2, 0x1) 1145 #define USART2_RX_PC2 SILABS_DBUS_USART2_RX(0x2, 0x2) 1146 #define USART2_RX_PC3 SILABS_DBUS_USART2_RX(0x2, 0x3) 1147 #define USART2_RX_PC4 SILABS_DBUS_USART2_RX(0x2, 0x4) 1148 #define USART2_RX_PC5 SILABS_DBUS_USART2_RX(0x2, 0x5) 1149 #define USART2_RX_PD0 SILABS_DBUS_USART2_RX(0x3, 0x0) 1150 #define USART2_RX_PD1 SILABS_DBUS_USART2_RX(0x3, 0x1) 1151 #define USART2_RX_PD2 SILABS_DBUS_USART2_RX(0x3, 0x2) 1152 #define USART2_RX_PD3 SILABS_DBUS_USART2_RX(0x3, 0x3) 1153 #define USART2_RX_PD4 SILABS_DBUS_USART2_RX(0x3, 0x4) 1154 #define USART2_CLK_PC0 SILABS_DBUS_USART2_CLK(0x2, 0x0) 1155 #define USART2_CLK_PC1 SILABS_DBUS_USART2_CLK(0x2, 0x1) 1156 #define USART2_CLK_PC2 SILABS_DBUS_USART2_CLK(0x2, 0x2) 1157 #define USART2_CLK_PC3 SILABS_DBUS_USART2_CLK(0x2, 0x3) 1158 #define USART2_CLK_PC4 SILABS_DBUS_USART2_CLK(0x2, 0x4) 1159 #define USART2_CLK_PC5 SILABS_DBUS_USART2_CLK(0x2, 0x5) 1160 #define USART2_CLK_PD0 SILABS_DBUS_USART2_CLK(0x3, 0x0) 1161 #define USART2_CLK_PD1 SILABS_DBUS_USART2_CLK(0x3, 0x1) 1162 #define USART2_CLK_PD2 SILABS_DBUS_USART2_CLK(0x3, 0x2) 1163 #define USART2_CLK_PD3 SILABS_DBUS_USART2_CLK(0x3, 0x3) 1164 #define USART2_CLK_PD4 SILABS_DBUS_USART2_CLK(0x3, 0x4) 1165 #define USART2_TX_PC0 SILABS_DBUS_USART2_TX(0x2, 0x0) 1166 #define USART2_TX_PC1 SILABS_DBUS_USART2_TX(0x2, 0x1) 1167 #define USART2_TX_PC2 SILABS_DBUS_USART2_TX(0x2, 0x2) 1168 #define USART2_TX_PC3 SILABS_DBUS_USART2_TX(0x2, 0x3) 1169 #define USART2_TX_PC4 SILABS_DBUS_USART2_TX(0x2, 0x4) 1170 #define USART2_TX_PC5 SILABS_DBUS_USART2_TX(0x2, 0x5) 1171 #define USART2_TX_PD0 SILABS_DBUS_USART2_TX(0x3, 0x0) 1172 #define USART2_TX_PD1 SILABS_DBUS_USART2_TX(0x3, 0x1) 1173 #define USART2_TX_PD2 SILABS_DBUS_USART2_TX(0x3, 0x2) 1174 #define USART2_TX_PD3 SILABS_DBUS_USART2_TX(0x3, 0x3) 1175 #define USART2_TX_PD4 SILABS_DBUS_USART2_TX(0x3, 0x4) 1176 #define USART2_CTS_PC0 SILABS_DBUS_USART2_CTS(0x2, 0x0) 1177 #define USART2_CTS_PC1 SILABS_DBUS_USART2_CTS(0x2, 0x1) 1178 #define USART2_CTS_PC2 SILABS_DBUS_USART2_CTS(0x2, 0x2) 1179 #define USART2_CTS_PC3 SILABS_DBUS_USART2_CTS(0x2, 0x3) 1180 #define USART2_CTS_PC4 SILABS_DBUS_USART2_CTS(0x2, 0x4) 1181 #define USART2_CTS_PC5 SILABS_DBUS_USART2_CTS(0x2, 0x5) 1182 #define USART2_CTS_PD0 SILABS_DBUS_USART2_CTS(0x3, 0x0) 1183 #define USART2_CTS_PD1 SILABS_DBUS_USART2_CTS(0x3, 0x1) 1184 #define USART2_CTS_PD2 SILABS_DBUS_USART2_CTS(0x3, 0x2) 1185 #define USART2_CTS_PD3 SILABS_DBUS_USART2_CTS(0x3, 0x3) 1186 #define USART2_CTS_PD4 SILABS_DBUS_USART2_CTS(0x3, 0x4) 1187 1188 #endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG21_PINCTRL_H_ */ 1189
