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Searched refs:TIMER_CHCTL2_CHXEN (Results 1 – 1 of 1) sorted by relevance

/Zephyr-latest/drivers/pwm/
Dpwm_gd32.c51 #define TIMER_CHCTL2_CHXEN(ch) BIT(4U * (ch)) macro
77 TIMER_CHCTL2(config->reg) &= ~TIMER_CHCTL2_CHXEN(channel); in pwm_gd32_set_cycles()
111 if ((TIMER_CHCTL2(config->reg) & TIMER_CHCTL2_CHXEN(channel)) == 0U) { in pwm_gd32_set_cycles()
126 TIMER_CHCTL2(config->reg) |= TIMER_CHCTL2_CHXEN(channel); in pwm_gd32_set_cycles()