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Searched refs:T0 (Results 1 – 2 of 2) sorted by relevance

/Zephyr-latest/samples/kernel/metairq_dispatch/
DREADME.rst96 II: M0 T0 mirq 4478 disp 7478 proc 24336 real 24613
97 I: M8 T0 mirq 4273 disp 86983 proc 9824 real 16753
98 I: M10 T0 mirq 4273 disp 495455 proc 21177 real 28273
99 I: M11 T0 mirq 4273 disp 981565 proc 48337 real 48918
100 I: M14 T0 mirq 4273 disp 1403627 proc 7079 real 7690
101 I: M17 T0 mirq 4273 disp 1810028 proc 42143 real 42925
102 I: M19 T0 mirq 4273 disp 2369217 proc 42471 real 42925
103 I: M20 T0 mirq 4273 disp 2940429 proc 30427 real 30775
104 I: M21 T0 mirq 4273 disp 3524151 proc 35871 real 36850
105 I: M22 T0 mirq 4273 disp 4042148 proc 33738 real 34420
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/Zephyr-latest/scripts/coredump/gdbstubs/arch/
Drisc_v.py22 T0 = 5 variable in RegNum
80 self.registers[RegNum.T0] = tu[2]