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Searched refs:STM32_SRC_CKPER (Results 1 – 12 of 12) sorted by relevance

/Zephyr-latest/boards/st/stm32n6570_dk/
Dstm32n6570_dk_common.dtsi101 <&rcc STM32_SRC_CKPER ADC12_SEL(1)>;
110 <&rcc STM32_SRC_CKPER FDCAN_SEL(1)>;
118 <&rcc STM32_SRC_CKPER I2C1_SEL(1)>;
127 <&rcc STM32_SRC_CKPER I2C4_SEL(1)>;
136 <&rcc STM32_SRC_CKPER SPI5_SEL(1)>;
144 <&rcc STM32_SRC_CKPER USART1_SEL(1)>;
153 <&rcc STM32_SRC_CKPER USART2_SEL(1)>;
/Zephyr-latest/boards/st/nucleo_n657x0_q/
Dnucleo_n657x0_q_common.dtsi119 <&rcc STM32_SRC_CKPER ADC12_SEL(1)>;
128 <&rcc STM32_SRC_CKPER FDCAN_SEL(1)>;
136 <&rcc STM32_SRC_CKPER I2C1_SEL(1)>;
145 <&rcc STM32_SRC_CKPER I2C4_SEL(1)>;
154 <&rcc STM32_SRC_CKPER SPI5_SEL(1)>;
162 <&rcc STM32_SRC_CKPER USART1_SEL(1)>;
171 <&rcc STM32_SRC_CKPER USART3_SEL(1)>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/
Dspi1_per_ck_d1ppre_1.overlay25 <&rcc STM32_SRC_CKPER SPI123_SEL(4)>;
Dspi1_per_ck_hse.overlay26 <&rcc STM32_SRC_CKPER SPI123_SEL(4)>;
Dspi1_per_ck_hsi.overlay25 <&rcc STM32_SRC_CKPER SPI123_SEL(4)>;
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32n6_clock.h27 #define STM32_SRC_CKPER (STM32_SRC_PLL4 + 1) macro
28 #define STM32_SRC_IC1 (STM32_SRC_CKPER + 1)
Dstm32h7rs_clock.h40 #define STM32_SRC_CKPER (STM32_SRC_PLL3_S + 1) macro
Dstm32h7_clock.h35 #define STM32_SRC_CKPER (STM32_SRC_PLL3_R + 1) macro
Dstm32h5_clock.h39 #define STM32_SRC_CKPER (STM32_SRC_PLL3_R + 1) macro
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/
Dtest_stm32_clock_configuration.c77 } else if (pclken[1].bus == STM32_SRC_CKPER) { in ZTEST()
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_n6.c167 ((src_clk == STM32_SRC_CKPER) && IS_ENABLED(STM32_CKPER_ENABLED)) || in enabled_clock()
335 case STM32_SRC_CKPER: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_h7.c363 ((src_clk == STM32_SRC_CKPER) && IS_ENABLED(STM32_CKPER_ENABLED)) ||
527 case STM32_SRC_CKPER: