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Searched refs:STM32_PLL3_P1_DIVISOR (Results 1 – 2 of 2) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_n6.c101 pllout_div1 = STM32_PLL3_P1_DIVISOR; in get_pllout_frequency()
734 LL_RCC_PLL3_SetP1(STM32_PLL3_P1_DIVISOR); in set_up_plls()
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h281 #define STM32_PLL3_P1_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p1) macro