1 /*
2  * Copyright (c) 2020 Teslabs Engineering S.L.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SDRAM_H_
8 #define ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SDRAM_H_
9 
10 /* Number of column address bits */
11 #define STM32_FMC_SDRAM_NC_8 0x00000000UL
12 #define STM32_FMC_SDRAM_NC_9 0x00000001UL
13 #define STM32_FMC_SDRAM_NC_10 0x00000002UL
14 #define STM32_FMC_SDRAM_NC_11 0x00000003UL
15 
16 /* Number of row address bits */
17 #define STM32_FMC_SDRAM_NR_11 0x00000000UL
18 #define STM32_FMC_SDRAM_NR_12 0x00000004UL
19 #define STM32_FMC_SDRAM_NR_13 0x00000008UL
20 
21 /* Memory data bus width. */
22 #define STM32_FMC_SDRAM_MWID_8 0x00000000UL
23 #define STM32_FMC_SDRAM_MWID_16 0x00000010UL
24 #define STM32_FMC_SDRAM_MWID_32 0x00000020UL
25 
26 /* Number of internal banks */
27 #define STM32_FMC_SDRAM_NB_2 0x00000000UL
28 #define STM32_FMC_SDRAM_NB_4 0x00000040UL
29 
30 /* CAS Latency */
31 #define STM32_FMC_SDRAM_CAS_1 0x00000080UL
32 #define STM32_FMC_SDRAM_CAS_2 0x00000100UL
33 #define STM32_FMC_SDRAM_CAS_3 0x00000180UL
34 
35 /* SDRAM clock configuration */
36 #define STM32_FMC_SDRAM_SDCLK_DISABLE 0x00000000UL
37 #define STM32_FMC_SDRAM_SDCLK_PERIOD_2 0x00000800UL
38 #define STM32_FMC_SDRAM_SDCLK_PERIOD_3 0x00000C00UL
39 
40 /* Burst read */
41 #define STM32_FMC_SDRAM_RBURST_DISABLE 0x00000000UL
42 #define STM32_FMC_SDRAM_RBURST_ENABLE 0x00001000UL
43 
44 /* Read pipe */
45 #define STM32_FMC_SDRAM_RPIPE_0 0x00000000UL
46 #define STM32_FMC_SDRAM_RPIPE_1 0x00002000UL
47 #define STM32_FMC_SDRAM_RPIPE_2 0x00004000UL
48 
49 #endif
50