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Searched refs:SRSTCLR (Results 1 – 2 of 2) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_control_renesas_cpg_mssr.h80 #define SRSTCLR(i) (0x940 + (i) * 4) macro
100 #define SRSTCLR(i) (0x2C80 + (i) * 4) macro
Dclock_control_renesas_cpg_mssr.c22 rcar_cpg_write(base_address, SRSTCLR(reg), BIT(bit)); in rcar_cpg_reset()