Home
last modified time | relevance | path

Searched refs:SILABS_DBUS_CMU_CLKIN0 (Results 1 – 5 of 5) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/silabs/
Dxg21-pinctrl.h23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 10, 0, 0, 1) macro
183 #define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0)
184 #define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1)
185 #define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2)
186 #define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3)
187 #define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4)
188 #define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5)
189 #define CMU_CLKIN0_PD0 SILABS_DBUS_CMU_CLKIN0(0x3, 0x0)
190 #define CMU_CLKIN0_PD1 SILABS_DBUS_CMU_CLKIN0(0x3, 0x1)
191 #define CMU_CLKIN0_PD2 SILABS_DBUS_CMU_CLKIN0(0x3, 0x2)
[all …]
Dxg22-pinctrl.h19 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 4, 0, 0, 1) macro
164 #define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0)
165 #define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1)
166 #define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2)
167 #define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3)
168 #define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4)
169 #define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5)
170 #define CMU_CLKIN0_PC6 SILABS_DBUS_CMU_CLKIN0(0x2, 0x6)
171 #define CMU_CLKIN0_PC7 SILABS_DBUS_CMU_CLKIN0(0x2, 0x7)
172 #define CMU_CLKIN0_PD0 SILABS_DBUS_CMU_CLKIN0(0x3, 0x0)
[all …]
Dxg27-pinctrl.h21 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 7, 0, 0, 1) macro
195 #define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0)
196 #define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1)
197 #define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2)
198 #define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3)
199 #define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4)
200 #define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5)
201 #define CMU_CLKIN0_PC6 SILABS_DBUS_CMU_CLKIN0(0x2, 0x6)
202 #define CMU_CLKIN0_PC7 SILABS_DBUS_CMU_CLKIN0(0x2, 0x7)
203 #define CMU_CLKIN0_PD0 SILABS_DBUS_CMU_CLKIN0(0x3, 0x0)
[all …]
Dxg24-pinctrl.h23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 10, 0, 0, 1) macro
269 #define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0)
270 #define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1)
271 #define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2)
272 #define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3)
273 #define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4)
274 #define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5)
275 #define CMU_CLKIN0_PC6 SILABS_DBUS_CMU_CLKIN0(0x2, 0x6)
276 #define CMU_CLKIN0_PC7 SILABS_DBUS_CMU_CLKIN0(0x2, 0x7)
277 #define CMU_CLKIN0_PC8 SILABS_DBUS_CMU_CLKIN0(0x2, 0x8)
[all …]
Dxg23-pinctrl.h23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 22, 0, 0, 1) macro
292 #define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0)
293 #define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1)
294 #define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2)
295 #define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3)
296 #define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4)
297 #define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5)
298 #define CMU_CLKIN0_PC6 SILABS_DBUS_CMU_CLKIN0(0x2, 0x6)
299 #define CMU_CLKIN0_PC7 SILABS_DBUS_CMU_CLKIN0(0x2, 0x7)
300 #define CMU_CLKIN0_PC8 SILABS_DBUS_CMU_CLKIN0(0x2, 0x8)
[all …]