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Searched refs:SET_BITS (Results 1 – 4 of 4) sorted by relevance

/Zephyr-latest/drivers/dma/
Ddma_dw_common.h20 #define SET_BITS(b_hi, b_lo, x) \ macro
104 #define DW_CFGH_DST_PER_EXT(x) SET_BITS(31, 30, x)
105 #define DW_CFGH_SRC_PER_EXT(x) SET_BITS(29, 28, x)
106 #define DW_CFGH_DST_PER(x) SET_BITS(7, 4, x)
107 #define DW_CFGH_SRC_PER(x) SET_BITS(3, 0, x)
120 #define DW_CTLL_FC_P2P SET_BITS(21, 20, 3)
121 #define DW_CTLL_FC_P2M SET_BITS(21, 20, 2)
122 #define DW_CTLL_FC_M2P SET_BITS(21, 20, 1)
123 #define DW_CTLL_FC_M2M SET_BITS(21, 20, 0)
126 #define DW_CTLL_SRC_MSIZE(x) SET_BITS(16, 14, x)
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Ddma_intel_adsp_gpdma.c20 #define GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x)
26 #define GPDMA_OSEL(x) SET_BITS(25, 24, x)
/Zephyr-latest/drivers/sdhc/
Dintel_emmc_host.c262 SET_BITS(regs->clock_ctrl, EMMC_HOST_CLK_SDCLCK_FREQ_SEL_LOC, in emmc_clock_set()
264 SET_BITS(regs->clock_ctrl, EMMC_HOST_CLK_SDCLCK_FREQ_SEL_UPPER_LOC, in emmc_clock_set()
319 SET_BITS(regs->host_ctrl2, EMMC_HOST_CTRL2_UHS_MODE_SEL_LOC, in set_timing()
467 SET_BITS(regs->host_ctrl1, EMMC_HOST_CTRL1_DMA_SEL_LOC, in emmc_init_xfr()
470 SET_BITS(regs->host_ctrl1, EMMC_HOST_CTRL1_DMA_SEL_LOC, in emmc_init_xfr()
475 SET_BITS(regs->block_size, EMMC_HOST_DMA_BUF_SIZE_LOC, EMMC_HOST_DMA_BUF_SIZE_MASK, in emmc_init_xfr()
477 SET_BITS(regs->block_size, EMMC_HOST_BLOCK_SIZE_LOC, EMMC_HOST_BLOCK_SIZE_MASK, in emmc_init_xfr()
486 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_AUTO_CMD_EN_LOC, in emmc_init_xfr()
489 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_AUTO_CMD_EN_LOC, in emmc_init_xfr()
493 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_AUTO_CMD_EN_LOC, in emmc_init_xfr()
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Dintel_emmc_host.h173 #define SET_BITS(reg, pos, bit_width, val) \ macro