1 /*
2  * Copyright (c) 2024 Renesas Electronics Corporation
3  * SPDX-License-Identifier: Apache-2.0
4  */
5 
6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_RENESAS_RA_SDRAM_H_
7 #define ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_RENESAS_RA_SDRAM_H_
8 
9 #define SDRAM_TRAS_1CYCLES (1)
10 #define SDRAM_TRAS_2CYCLES (2)
11 #define SDRAM_TRAS_3CYCLES (3)
12 #define SDRAM_TRAS_4CYCLES (4)
13 #define SDRAM_TRAS_5CYCLES (5)
14 #define SDRAM_TRAS_6CYCLES (6)
15 #define SDRAM_TRAS_7CYCLES (7)
16 
17 #define SDRAM_TRCD_1CYCLES (1)
18 #define SDRAM_TRCD_2CYCLES (2)
19 #define SDRAM_TRCD_3CYCLES (3)
20 #define SDRAM_TRCD_4CYCLES (4)
21 
22 #define SDRAM_TRP_1CYCLES (1)
23 #define SDRAM_TRP_2CYCLES (2)
24 #define SDRAM_TRP_3CYCLES (3)
25 #define SDRAM_TRP_4CYCLES (4)
26 #define SDRAM_TRP_5CYCLES (5)
27 #define SDRAM_TRP_6CYCLES (6)
28 #define SDRAM_TRP_7CYCLES (7)
29 #define SDRAM_TRP_8CYCLES (8)
30 
31 #define SDRAM_TWR_1CYCLES (1)
32 #define SDRAM_TWR_2CYCLES (2)
33 
34 #define SDRAM_TCL_1CYCLES (1)
35 #define SDRAM_TCL_2CYCLES (2)
36 #define SDRAM_TCL_3CYCLES (3)
37 
38 #define SDRAM_TREFW_1CYCLES  (1)
39 #define SDRAM_TREFW_2CYCLES  (2)
40 #define SDRAM_TREFW_3CYCLES  (3)
41 #define SDRAM_TREFW_4CYCLES  (4)
42 #define SDRAM_TREFW_5CYCLES  (5)
43 #define SDRAM_TREFW_6CYCLES  (6)
44 #define SDRAM_TREFW_7CYCLES  (7)
45 #define SDRAM_TREFW_8CYCLES  (8)
46 #define SDRAM_TREFW_9CYCLES  (9)
47 #define SDRAM_TREFW_10CYCLES (10)
48 #define SDRAM_TREFW_11CYCLES (11)
49 #define SDRAM_TREFW_12CYCLES (12)
50 #define SDRAM_TREFW_13CYCLES (13)
51 #define SDRAM_TREFW_14CYCLES (14)
52 #define SDRAM_TREFW_15CYCLES (15)
53 #define SDRAM_TREFW_16CYCLES (16)
54 
55 #define SDRAM_AUTO_REFREDSH_INTERVEL_3CYCLES  (3)
56 #define SDRAM_AUTO_REFREDSH_INTERVEL_4CYCLES  (4)
57 #define SDRAM_AUTO_REFREDSH_INTERVEL_5CYCLES  (5)
58 #define SDRAM_AUTO_REFREDSH_INTERVEL_6CYCLES  (6)
59 #define SDRAM_AUTO_REFREDSH_INTERVEL_7CYCLES  (7)
60 #define SDRAM_AUTO_REFREDSH_INTERVEL_8CYCLES  (8)
61 #define SDRAM_AUTO_REFREDSH_INTERVEL_9CYCLES  (9)
62 #define SDRAM_AUTO_REFREDSH_INTERVEL_10CYCLES (10)
63 #define SDRAM_AUTO_REFREDSH_INTERVEL_11CYCLES (11)
64 #define SDRAM_AUTO_REFREDSH_INTERVEL_12CYCLES (12)
65 #define SDRAM_AUTO_REFREDSH_INTERVEL_13CYCLES (13)
66 #define SDRAM_AUTO_REFREDSH_INTERVEL_14CYCLES (14)
67 #define SDRAM_AUTO_REFREDSH_INTERVEL_15CYCLES (15)
68 #define SDRAM_AUTO_REFREDSH_INTERVEL_16CYCLES (16)
69 #define SDRAM_AUTO_REFREDSH_INTERVEL_17CYCLES (17)
70 #define SDRAM_AUTO_REFREDSH_INTERVEL_18CYCLES (18)
71 #define SDRAM_AUTO_REFREDSH_INTERVEL_19CYCLES (19)
72 #define SDRAM_AUTO_REFREDSH_INTERVEL_20CYCLES (20)
73 
74 #define SDRAM_AUTO_REFREDSH_COUNT_1TIMES  (1)
75 #define SDRAM_AUTO_REFREDSH_COUNT_2TIMES  (2)
76 #define SDRAM_AUTO_REFREDSH_COUNT_3TIMES  (3)
77 #define SDRAM_AUTO_REFREDSH_COUNT_4TIMES  (4)
78 #define SDRAM_AUTO_REFREDSH_COUNT_5TIMES  (5)
79 #define SDRAM_AUTO_REFREDSH_COUNT_6TIMES  (6)
80 #define SDRAM_AUTO_REFREDSH_COUNT_7TIMES  (7)
81 #define SDRAM_AUTO_REFREDSH_COUNT_8TIMES  (8)
82 #define SDRAM_AUTO_REFREDSH_COUNT_9TIMES  (9)
83 #define SDRAM_AUTO_REFREDSH_COUNT_10TIMES (10)
84 #define SDRAM_AUTO_REFREDSH_COUNT_11TIMES (11)
85 #define SDRAM_AUTO_REFREDSH_COUNT_12TIMES (12)
86 #define SDRAM_AUTO_REFREDSH_COUNT_13TIMES (13)
87 #define SDRAM_AUTO_REFREDSH_COUNT_14TIMES (14)
88 #define SDRAM_AUTO_REFREDSH_COUNT_15TIMES (15)
89 
90 #define SDRAM_AUTO_PRECHARGE_CYCLE_3CYCLES  (3)
91 #define SDRAM_AUTO_PRECHARGE_CYCLE_4CYCLES  (4)
92 #define SDRAM_AUTO_PRECHARGE_CYCLE_5CYCLES  (5)
93 #define SDRAM_AUTO_PRECHARGE_CYCLE_6CYCLES  (6)
94 #define SDRAM_AUTO_PRECHARGE_CYCLE_7CYCLES  (7)
95 #define SDRAM_AUTO_PRECHARGE_CYCLE_8CYCLES  (8)
96 #define SDRAM_AUTO_PRECHARGE_CYCLE_9CYCLES  (9)
97 #define SDRAM_AUTO_PRECHARGE_CYCLE_10CYCLES (10)
98 
99 #endif
100