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Searched refs:SCTLR_EL3_RES1 (Results 1 – 2 of 2) sorted by relevance

/Zephyr-latest/include/zephyr/arch/arm64/
Dcpu.h39 #define SCTLR_EL3_RES1 (BIT(29) | BIT(28) | BIT(23) | \ macro
/Zephyr-latest/arch/arm64/core/
Dreset.S48 ldr w0, =(SCTLR_EL3_RES1 | SCTLR_I_BIT | SCTLR_SA_BIT)