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Searched refs:RISCV_MCAUSE_IRQ_POS (Results 1 – 3 of 3) sorted by relevance

/Zephyr-latest/include/zephyr/arch/riscv/
Dirq.h44 #define RISCV_MCAUSE_IRQ_POS 63U macro
45 #define RISCV_MCAUSE_IRQ_BIT BIT64(RISCV_MCAUSE_IRQ_POS)
47 #define RISCV_MCAUSE_IRQ_POS 31U
48 #define RISCV_MCAUSE_IRQ_BIT BIT(RISCV_MCAUSE_IRQ_POS)
/Zephyr-latest/soc/nordic/common/vpr/
Dsoc_isr_stacking.h109 srli t0, t0, RISCV_MCAUSE_IRQ_POS; \
127 srli t0, t0, RISCV_MCAUSE_IRQ_POS; \
/Zephyr-latest/arch/riscv/core/
Disr.S333 srli t0, t0, RISCV_MCAUSE_IRQ_POS