1 /*
2 * Copyright (c) 2021 IoT.bzh
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT renesas_rcar_i2c
8
9 #include <errno.h>
10 #include <zephyr/device.h>
11 #include <zephyr/devicetree.h>
12 #include <zephyr/drivers/i2c.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
15
16 #include <zephyr/logging/log.h>
17 #include <zephyr/irq.h>
18 LOG_MODULE_REGISTER(i2c_rcar);
19
20 #include "i2c-priv.h"
21
22 typedef void (*init_func_t)(const struct device *dev);
23
24 struct i2c_rcar_cfg {
25 uint32_t reg_addr;
26 init_func_t init_func;
27 const struct device *clock_dev;
28 struct rcar_cpg_clk mod_clk;
29 uint32_t bitrate;
30 };
31
32 struct i2c_rcar_data {
33 uint8_t status_mask;
34 struct k_sem int_sem;
35 };
36
37 /* Registers */
38 #define RCAR_I2C_ICSCR 0x00 /* Slave Control Register */
39 #define RCAR_I2C_ICMCR 0x04 /* Master Control Register */
40 #define RCAR_I2C_ICSIER 0x10 /* Slave IRQ Enable */
41 #define RCAR_I2C_ICMIER 0x14 /* Master IRQ Enable */
42 #define RCAR_I2C_ICSSR 0x08 /* Slave Status */
43 #define RCAR_I2C_ICMSR 0x0c /* Master Status */
44 #define RCAR_I2C_ICCCR 0x18 /* Clock Control Register */
45 #define RCAR_I2C_ICSAR 0x1c /* Slave Address Register */
46 #define RCAR_I2C_ICMAR 0x20 /* Master Address Register */
47 #define RCAR_I2C_ICRXD_ICTXD 0x24 /* Receive Transmit Data Register */
48 #define RCAR_I2C_ICFBSCR 0x38 /* First Bit Setup Cycle (Gen3).*/
49 #define RCAR_I2C_ICFBSCR_TCYC17 0x0f /* 17*Tcyc */
50
51 #define RCAR_I2C_ICMCR_MDBS BIT(7) /* Master Data Buffer Select */
52 #define RCAR_I2C_ICMCR_FSCL BIT(6) /* Forced SCL */
53 #define RCAR_I2C_ICMCR_FSDA BIT(5) /* Forced SDA */
54 #define RCAR_I2C_ICMCR_OBPC BIT(4) /* Override Bus Pin Control */
55 #define RCAR_I2C_ICMCR_MIE BIT(3) /* Master Interface Enable */
56 #define RCAR_I2C_ICMCR_TSBE BIT(2) /* Start Byte Transmission Enable */
57 #define RCAR_I2C_ICMCR_FSB BIT(1) /* Forced Stop onto the Bus */
58 #define RCAR_I2C_ICMCR_ESG BIT(0) /* Enable Start Generation */
59 #define RCAR_I2C_ICMCR_MASTER (RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE)
60
61 /* Bits to manage ICMIER and ICMSR registers */
62 #define RCAR_I2C_MNR BIT(6) /* Master Nack Received */
63 #define RCAR_I2C_MAL BIT(5) /* Master Arbitration lost */
64 #define RCAR_I2C_MST BIT(4) /* Master Stop Transmitted */
65 #define RCAR_I2C_MDE BIT(3) /* Master Data Empty */
66 #define RCAR_I2C_MDT BIT(2) /* Master Data Transmitted */
67 #define RCAR_I2C_MDR BIT(1) /* Master Data Received */
68 #define RCAR_I2C_MAT BIT(0) /* Master Address Transmitted */
69
70 /* Recommended bitrate settings from official documentation */
71 #define RCAR_I2C_ICCCR_CDF_100_KHZ 6
72 #define RCAR_I2C_ICCCR_CDF_400_KHZ 6
73 #define RCAR_I2C_ICCCR_SCGD_100_KHZ 21
74 #define RCAR_I2C_ICCCR_SCGD_400_KHZ 3
75
76 #define MAX_WAIT_US 100
77
i2c_rcar_read(const struct i2c_rcar_cfg * config,uint32_t offs)78 static uint32_t i2c_rcar_read(const struct i2c_rcar_cfg *config,
79 uint32_t offs)
80 {
81 return sys_read32(config->reg_addr + offs);
82 }
83
i2c_rcar_write(const struct i2c_rcar_cfg * config,uint32_t offs,uint32_t value)84 static void i2c_rcar_write(const struct i2c_rcar_cfg *config,
85 uint32_t offs, uint32_t value)
86 {
87 sys_write32(value, config->reg_addr + offs);
88 }
89
i2c_rcar_isr(const struct device * dev)90 static void i2c_rcar_isr(const struct device *dev)
91 {
92 const struct i2c_rcar_cfg *config = dev->config;
93 struct i2c_rcar_data *data = dev->data;
94
95 if (((i2c_rcar_read(config, RCAR_I2C_ICMSR)) & data->status_mask) ==
96 data->status_mask) {
97 k_sem_give(&data->int_sem);
98 i2c_rcar_write(config, RCAR_I2C_ICMIER, 0);
99 }
100 }
101
i2c_rcar_wait_for_state(const struct device * dev,uint8_t mask)102 static int i2c_rcar_wait_for_state(const struct device *dev, uint8_t mask)
103 {
104 const struct i2c_rcar_cfg *config = dev->config;
105 struct i2c_rcar_data *data = dev->data;
106
107 data->status_mask = mask;
108
109 /* Reset interrupts semaphore */
110 k_sem_reset(&data->int_sem);
111
112 /* Enable interrupts */
113 i2c_rcar_write(config, RCAR_I2C_ICMIER, mask);
114
115 /* Wait for the interrupts */
116 return k_sem_take(&data->int_sem, K_USEC(MAX_WAIT_US));
117 }
118
i2c_rcar_finish(const struct device * dev)119 static int i2c_rcar_finish(const struct device *dev)
120 {
121 const struct i2c_rcar_cfg *config = dev->config;
122 int ret;
123
124 /* Enable STOP generation */
125 i2c_rcar_write(config, RCAR_I2C_ICMCR, RCAR_I2C_ICMCR_MASTER | RCAR_I2C_ICMCR_FSB);
126 i2c_rcar_write(config, RCAR_I2C_ICMSR, 0);
127
128 /* Wait for STOP to be transmitted */
129 ret = i2c_rcar_wait_for_state(dev, RCAR_I2C_MST);
130 i2c_rcar_write(config, RCAR_I2C_ICMSR, 0);
131
132 /* Disable STOP generation */
133 i2c_rcar_write(config, RCAR_I2C_ICMCR, RCAR_I2C_ICMCR_MASTER);
134
135 return ret;
136 }
137
i2c_rcar_set_addr(const struct device * dev,uint8_t chip,uint8_t read)138 static int i2c_rcar_set_addr(const struct device *dev,
139 uint8_t chip, uint8_t read)
140 {
141 const struct i2c_rcar_cfg *config = dev->config;
142
143 /* Set slave address & transfer mode */
144 i2c_rcar_write(config, RCAR_I2C_ICMAR, (chip << 1) | read);
145 /* Reset */
146 i2c_rcar_write(config, RCAR_I2C_ICMCR, RCAR_I2C_ICMCR_MASTER | RCAR_I2C_ICMCR_ESG);
147 /* Clear Status */
148 i2c_rcar_write(config, RCAR_I2C_ICMSR, 0);
149
150 /* Wait for address & transfer mode to be transmitted */
151 if (read != 0) {
152 return i2c_rcar_wait_for_state(dev, RCAR_I2C_MAT | RCAR_I2C_MDR);
153 } else {
154 return i2c_rcar_wait_for_state(dev, RCAR_I2C_MAT | RCAR_I2C_MDE);
155 }
156 }
157
i2c_rcar_transfer_msg(const struct device * dev,struct i2c_msg * msg)158 static int i2c_rcar_transfer_msg(const struct device *dev, struct i2c_msg *msg)
159 {
160 const struct i2c_rcar_cfg *config = dev->config;
161 uint32_t i, reg;
162 int ret = 0;
163
164 if ((msg->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
165 /* Reading as master */
166 i2c_rcar_write(config, RCAR_I2C_ICMCR, RCAR_I2C_ICMCR_MASTER);
167
168 for (i = 0; i < msg->len; i++) {
169 if (msg->len - 1 == i) {
170 i2c_rcar_write(config, RCAR_I2C_ICMCR, RCAR_I2C_ICMCR_MASTER |
171 RCAR_I2C_ICMCR_FSB);
172 }
173
174 /* Start data reception */
175 reg = i2c_rcar_read(config, RCAR_I2C_ICMSR);
176 reg &= ~RCAR_I2C_MDR;
177 i2c_rcar_write(config, RCAR_I2C_ICMSR, reg);
178
179 /* Wait for data to be received */
180 ret = i2c_rcar_wait_for_state(dev, RCAR_I2C_MDR);
181 if (ret != 0) {
182 return ret;
183 }
184
185 msg->buf[i] = i2c_rcar_read(config, RCAR_I2C_ICRXD_ICTXD) & 0xff;
186 }
187 } else {
188 /* Writing as master */
189 for (i = 0; i < msg->len; i++) {
190 i2c_rcar_write(config, RCAR_I2C_ICRXD_ICTXD, msg->buf[i]);
191
192 i2c_rcar_write(config, RCAR_I2C_ICMCR, RCAR_I2C_ICMCR_MASTER);
193
194 /* Start data transmission */
195 reg = i2c_rcar_read(config, RCAR_I2C_ICMSR);
196 reg &= ~RCAR_I2C_MDE;
197 i2c_rcar_write(config, RCAR_I2C_ICMSR, reg);
198
199 /* Wait for all data to be transmitted */
200 ret = i2c_rcar_wait_for_state(dev, RCAR_I2C_MDE);
201 if (ret != 0) {
202 return ret;
203 }
204 }
205 }
206
207 return ret;
208 }
209
i2c_rcar_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t addr)210 static int i2c_rcar_transfer(const struct device *dev,
211 struct i2c_msg *msgs, uint8_t num_msgs,
212 uint16_t addr)
213 {
214 const struct i2c_rcar_cfg *config = dev->config;
215 uint16_t timeout = 0;
216 int ret;
217
218 if (!num_msgs) {
219 return 0;
220 }
221
222 /* Wait for the bus to be available */
223 while ((i2c_rcar_read(config, RCAR_I2C_ICMCR) & RCAR_I2C_ICMCR_FSDA) && (timeout < 10)) {
224 k_busy_wait(USEC_PER_MSEC);
225 timeout++;
226 }
227 if (timeout == 10) {
228 return -EIO;
229 }
230
231 do {
232 /* We are not supporting 10-bit addressing */
233 if ((msgs->flags & I2C_MSG_ADDR_10_BITS) == I2C_MSG_ADDR_10_BITS) {
234 return -ENOTSUP;
235 }
236
237 /* Send slave address */
238 if (i2c_rcar_set_addr(dev, addr, !!(msgs->flags & I2C_MSG_READ))) {
239 return -EIO; /* No ACK received */
240 }
241
242 /* Transfer data */
243 if (msgs->len) {
244 ret = i2c_rcar_transfer_msg(dev, msgs);
245 if (ret != 0) {
246 return ret;
247 }
248 }
249
250 /* Finish the transfer */
251 if ((msgs->flags & I2C_MSG_STOP) == I2C_MSG_STOP) {
252 ret = i2c_rcar_finish(dev);
253 if (ret != 0) {
254 return ret;
255 }
256 }
257
258 /* Next message */
259 msgs++;
260 num_msgs--;
261 } while (num_msgs);
262
263 /* Complete without error */
264 return 0;
265 }
266
i2c_rcar_configure(const struct device * dev,uint32_t dev_config)267 static int i2c_rcar_configure(const struct device *dev, uint32_t dev_config)
268 {
269 const struct i2c_rcar_cfg *config = dev->config;
270 uint8_t cdf, scgd;
271
272 /* We only support Master mode */
273 if ((dev_config & I2C_MODE_CONTROLLER) != I2C_MODE_CONTROLLER) {
274 return -ENOTSUP;
275 }
276
277 /* We are not supporting 10-bit addressing */
278 if ((dev_config & I2C_ADDR_10_BITS) == I2C_ADDR_10_BITS) {
279 return -ENOTSUP;
280 }
281
282 switch (I2C_SPEED_GET(dev_config)) {
283 case I2C_SPEED_STANDARD:
284 /* Use recommended value for 100 kHz bus */
285 cdf = RCAR_I2C_ICCCR_CDF_100_KHZ;
286 scgd = RCAR_I2C_ICCCR_SCGD_100_KHZ;
287 break;
288 case I2C_SPEED_FAST:
289 /* Use recommended value for 400 kHz bus */
290 cdf = RCAR_I2C_ICCCR_CDF_400_KHZ;
291 scgd = RCAR_I2C_ICCCR_SCGD_400_KHZ;
292 break;
293 default:
294 return -ENOTSUP;
295 }
296
297 /* Setting ICCCR to recommended value */
298 i2c_rcar_write(config, RCAR_I2C_ICCCR, (scgd << 3) | cdf);
299
300 /* Reset slave mode */
301 i2c_rcar_write(config, RCAR_I2C_ICSIER, 0);
302 i2c_rcar_write(config, RCAR_I2C_ICSAR, 0);
303 i2c_rcar_write(config, RCAR_I2C_ICSCR, 0);
304 i2c_rcar_write(config, RCAR_I2C_ICSSR, 0);
305
306 /* Reset master mode */
307 i2c_rcar_write(config, RCAR_I2C_ICMIER, 0);
308 i2c_rcar_write(config, RCAR_I2C_ICMCR, 0);
309 i2c_rcar_write(config, RCAR_I2C_ICMSR, 0);
310 i2c_rcar_write(config, RCAR_I2C_ICMAR, 0);
311
312 return 0;
313 }
314
i2c_rcar_init(const struct device * dev)315 static int i2c_rcar_init(const struct device *dev)
316 {
317 const struct i2c_rcar_cfg *config = dev->config;
318 struct i2c_rcar_data *data = dev->data;
319 uint32_t bitrate_cfg;
320 int ret;
321
322 k_sem_init(&data->int_sem, 0, 1);
323
324 if (!device_is_ready(config->clock_dev)) {
325 return -ENODEV;
326 }
327
328 ret = clock_control_on(config->clock_dev,
329 (clock_control_subsys_t)&config->mod_clk);
330
331 if (ret != 0) {
332 return ret;
333 }
334
335 bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
336
337 ret = i2c_rcar_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
338 if (ret != 0) {
339 return ret;
340 }
341
342 config->init_func(dev);
343
344 return 0;
345 }
346
347 static DEVICE_API(i2c, i2c_rcar_driver_api) = {
348 .configure = i2c_rcar_configure,
349 .transfer = i2c_rcar_transfer,
350 #ifdef CONFIG_I2C_RTIO
351 .iodev_submit = i2c_iodev_submit_fallback,
352 #endif
353 };
354
355 /* Device Instantiation */
356 #define I2C_RCAR_INIT(n) \
357 static void i2c_rcar_##n##_init(const struct device *dev); \
358 static const struct i2c_rcar_cfg i2c_rcar_cfg_##n = { \
359 .reg_addr = DT_INST_REG_ADDR(n), \
360 .init_func = i2c_rcar_##n##_init, \
361 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
362 .bitrate = DT_INST_PROP(n, clock_frequency), \
363 .mod_clk.module = \
364 DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module), \
365 .mod_clk.domain = \
366 DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain), \
367 }; \
368 \
369 static struct i2c_rcar_data i2c_rcar_data_##n; \
370 \
371 I2C_DEVICE_DT_INST_DEFINE(n, \
372 i2c_rcar_init, \
373 NULL, \
374 &i2c_rcar_data_##n, \
375 &i2c_rcar_cfg_##n, \
376 POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
377 &i2c_rcar_driver_api \
378 ); \
379 static void i2c_rcar_##n##_init(const struct device *dev) \
380 { \
381 IRQ_CONNECT(DT_INST_IRQN(n), \
382 0, \
383 i2c_rcar_isr, \
384 DEVICE_DT_INST_GET(n), 0); \
385 \
386 irq_enable(DT_INST_IRQN(n)); \
387 }
388
389 DT_INST_FOREACH_STATUS_OKAY(I2C_RCAR_INIT)
390
