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Searched refs:RAM_ADDR (Results 1 – 8 of 8) sorted by relevance

/Zephyr-latest/include/zephyr/linker/
Dlinker-devnull.h24 #if (!defined(RAM_ADDR) && !defined(RAM_BASE)) || !defined(RAM_SIZE)
32 #if !defined(RAM_ADDR)
33 #define RAM_ADDR RAM_BASE macro
52 #if RAM_ADDR >= DEVNULL_SIZE
53 #define DEVNULL_ADDR (RAM_ADDR - DEVNULL_SIZE)
55 #define DEVNULL_ADDR (RAM_ADDR + RAM_SIZE)
60 #if ((ROM_ADDR > RAM_ADDR) && ((MAX_ADDR - ROM_END_ADDR) >= DEVNULL_SIZE)) || \
61 ((ROM_END_ADDR + DEVNULL_SIZE) <= RAM_ADDR)
/Zephyr-latest/tests/drivers/i2c/i2c_ram/src/
Dtest_i2c_ram.c21 #define RAM_ADDR (0b10100010 >> 1) macro
98 zassert_ok(i2c_transfer(i2c_dev, msgs, 1, RAM_ADDR), in ZTEST()
109 zassert_ok(i2c_transfer(i2c_dev, msgs, 2, RAM_ADDR), in ZTEST()
121 zassert_ok(i2c_write(i2c_dev, tx_data, ARRAY_SIZE(tx_data), RAM_ADDR), in ZTEST()
124 zassert_ok(i2c_write_read(i2c_dev, RAM_ADDR, rx_cmd, ARRAY_SIZE(rx_cmd), in ZTEST()
149 zassert_ok(i2c_transfer_cb(i2c_dev, msgs, 1, RAM_ADDR, in ZTEST()
163 zassert_ok(i2c_transfer_cb(i2c_dev, msgs, 2, RAM_ADDR, in ZTEST()
178 I2C_IODEV_DEFINE(i2c_iodev, I2C_DEV_NODE, RAM_ADDR);
/Zephyr-latest/cmake/linker_script/arm/
Dlinker.cmake31 set(RAM_ADDR ${CONFIG_SRAM_BASE_ADDRESS}) variable
33 math(EXPR IDT_ADDR "${RAM_ADDR} + ${RAM_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
41 zephyr_linker_memory(NAME RAM FLAGS wx START ${RAM_ADDR} SIZE ${RAM_SIZE})
55 set(rom_start ${RAM_ADDR})
148 zephyr_linker_symbol(SYMBOL __kernel_ram_end EXPR "(${RAM_ADDR} + ${RAM_SIZE})")
150 zephyr_linker_symbol(SYMBOL _image_ram_start EXPR "(${RAM_ADDR})" SUBALIGN 32) # ToDo calculate 32…
151 zephyr_linker_symbol(SYMBOL ARM_LIB_STACKHEAP EXPR "(${RAM_ADDR} + ${RAM_SIZE})" SIZE -0x1000)
/Zephyr-latest/include/zephyr/arch/arm64/scripts/
Dlinker.ld30 #define ROM_ADDR RAM_ADDR
48 #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS macro
69 RAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
216 . = RAM_ADDR;
289 __kernel_ram_end = RAM_ADDR + RAM_SIZE;
/Zephyr-latest/include/zephyr/arch/arm/cortex_a_r/scripts/
Dlinker.ld38 #define ROM_ADDR RAM_ADDR
56 #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS macro
89 RAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
124 __rom_region_start = RAM_ADDR;
260 . = RAM_ADDR;
351 __kernel_ram_end = RAM_ADDR + RAM_SIZE;
/Zephyr-latest/soc/infineon/cat1b/cyw20829/
Dlinker.ld31 #define ROM_ADDR RAM_ADDR
49 #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS macro
79 RAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
243 . = RAM_ADDR;
379 __kernel_ram_end = RAM_ADDR + RAM_SIZE;
/Zephyr-latest/include/zephyr/arch/arm/cortex_m/scripts/
Dlinker.ld38 #define ROM_ADDR RAM_ADDR
56 #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS macro
89 RAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
260 . = RAM_ADDR;
453 __kernel_ram_end = RAM_ADDR + RAM_SIZE;
/Zephyr-latest/soc/nuvoton/npcx/common/ecst/
Decst_args.py63 RAM_ADDR = 0x00 variable