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Searched refs:R8A779F0_CLK_SD0_DIV_MASK (Results 1 – 1 of 1) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_control_r8a779f0_cpg_mssr.c26 #define R8A779F0_CLK_SD0_DIV_MASK 0x3 macro
196 return (1 << ((reg_val & R8A779F0_CLK_SD0_DIV_MASK) + 1)); in r8a779f0_get_div_helper()
220 *div_mask = R8A779F0_CLK_SD0_DIV_MASK << R8A779F0_CLK_SD0_DIV_SHIFT; in r8a779f0_set_rate_helper()