1 /* 2 * Copyright (c) 2021 Katsuhiro Suzuki 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _SIFIVE_FU540_PRCI_H 8 #define _SIFIVE_FU540_PRCI_H 9 10 /* Clock controller. */ 11 #define PRCI_BASE_ADDR 0x10000000UL 12 13 #define Z_REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) 14 #define PRCI_REG(offset) Z_REG32(PRCI_BASE_ADDR, offset) 15 16 /* Register offsets */ 17 18 #define PRCI_HFXOSCCFG (0x0000) 19 #define PRCI_COREPLLCFG0 (0x0004) 20 #define PRCI_DDRPLLCFG0 (0x000c) 21 #define PRCI_DDRPLLCFG1 (0x0010) 22 #define PRCI_GEMGXLPLLCFG0 (0x001c) 23 #define PRCI_GEMGXLPLLCFG1 (0x0020) 24 #define PRCI_CORECLKSEL (0x0024) 25 #define PRCI_DEVICESRESETREG (0x0028) 26 27 #define PLL_R(x) (((x) & 0x3f) << 0) 28 #define PLL_F(x) (((x) & 0x1ff) << 6) 29 #define PLL_Q(x) (((x) & 0x7) << 15) 30 #define PLL_RANGE(x) (((x) & 0x7) << 18) 31 #define PLL_BYPASS(x) (((x) & 0x1) << 24) 32 #define PLL_FSE(x) (((x) & 0x1) << 25) 33 #define PLL_LOCK(x) (((x) & 0x1) << 31) 34 35 #define PLL_RANGE_33MHZ 4 36 #define PLL_BYPASS_DISABLE 0 37 #define PLL_BYPASS_ENABLE 1 38 #define PLL_FSE_INTERNAL 1 39 40 #define CORECLKSEL_CORECLKSEL(x) (((x) & 0x1) << 0) 41 42 #define CORECLKSEL_CORE_PLL 0 43 #define CORECLKSEL_HFCLK 1 44 45 #endif /* _SIFIVE_FU540_PRCI_H */ 46