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Searched refs:PLL_FINAL_DIV_BY_1 (Results 1 – 2 of 2) sorted by relevance

/Zephyr-latest/soc/sifive/sifive_freedom/fe300/
Dclock.c55 PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); in soc_early_init_hook()
Dprci.h53 #define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1) << 8) macro