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Searched refs:PHY_MRVL_GENERAL_CONTROL_1_RESET_BIT (Results 1 – 2 of 2) sorted by relevance

/Zephyr-latest/drivers/ethernet/
Dphy_xlnx_gem.h46 #define PHY_MRVL_GENERAL_CONTROL_1_RESET_BIT (1 << 15) macro
Dphy_xlnx_gem.c283 phy_data |= PHY_MRVL_GENERAL_CONTROL_1_RESET_BIT; in phy_xlnx_gem_marvell_alaska_cfg()
288 while (((phy_data & PHY_MRVL_GENERAL_CONTROL_1_RESET_BIT) != 0) && in phy_xlnx_gem_marvell_alaska_cfg()