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Searched refs:PHY_DQ_TIMING_REG_OFFSET (Results 1 – 2 of 2) sorted by relevance

/Zephyr-latest/drivers/flash/
Dflash_cadence_nand_ll.h237 #define PHY_DQ_TIMING_REG_OFFSET (0x00002000) macro
Dflash_cadence_nand_ll.c231 sys_write32(PHY_DQ_TIMING_REG_SDR, (base_address + PHY_DQ_TIMING_REG_OFFSET)); in cdns_nand_set_opr_mode()
253 sys_write32(PHY_DQ_TIMING_REG_DDR, (base_address + PHY_DQ_TIMING_REG_OFFSET)); in cdns_nand_set_opr_mode()