Searched refs:PHY_DQS_TIMING_REG_DDR (Results 1 – 2 of 2) sorted by relevance
255 #define PHY_DQS_TIMING_REG_DDR (0x00000004) macro
254 sys_write32(PHY_DQS_TIMING_REG_DDR, (base_address + PHY_DQS_TIMING_REG_OFFSET)); in cdns_nand_set_opr_mode()
