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Searched refs:PHY_DLL_MASTER_CTRL_REG_DDR (Results 1 – 2 of 2) sorted by relevance

/Zephyr-latest/drivers/flash/
Dflash_cadence_nand_ll.h257 #define PHY_DLL_MASTER_CTRL_REG_DDR (0x001400fe) macro
Dflash_cadence_nand_ll.c256 sys_write32(PHY_DLL_MASTER_CTRL_REG_DDR, (base_address + PHY_DLL_MASTER_OFFSET)); in cdns_nand_set_opr_mode()