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Searched refs:NUM_CHANNELS (Results 1 – 4 of 4) sorted by relevance

/Zephyr-latest/drivers/counter/
Dcounter_mcux_ctimer.c19 #define NUM_CHANNELS 3 macro
21 #define NUM_CHANNELS 4 macro
30 struct mcux_lpc_ctimer_channel_data channels[NUM_CHANNELS];
84 if (base->MR[NUM_CHANNELS] != 0) { in mcux_lpc_ctimer_get_top_value()
85 return base->MR[NUM_CHANNELS]; in mcux_lpc_ctimer_get_top_value()
182 CTIMER_SetupMatch(config->base, NUM_CHANNELS, &match_config); in mcux_lpc_ctimer_set_top_value()
229 for (uint8_t chan = 0; chan < NUM_CHANNELS; chan++) { in mcux_lpc_ctimer_isr()
245 if (((interrupt_stat & (0x01 << NUM_CHANNELS)) != 0) && data->top_callback) { in mcux_lpc_ctimer_isr()
262 for (uint8_t chan = 0; chan < NUM_CHANNELS; chan++) { in mcux_lpc_ctimer_init()
298 .channels = NUM_CHANNELS, \
/Zephyr-latest/drivers/pwm/
Dpwm_xmc4xxx_ccu8.c21 #define NUM_CHANNELS (NUM_SLICES * 2) macro
32 const uint32_t deadtime_high_ns[NUM_CHANNELS];
33 const uint32_t deadtime_low_ns[NUM_CHANNELS];
97 if (channel >= NUM_CHANNELS) { in pwm_xmc4xxx_ccu8_set_cycles()
142 if (channel >= NUM_CHANNELS) { in pwm_xmc4xxx_ccu8_get_cycles_per_sec()
Dpwm_xmc4xxx_ccu4.c21 #define NUM_CHANNELS NUM_SLICES macro
59 if (channel >= NUM_CHANNELS) { in pwm_xmc4xxx_ccu4_set_cycles()
/Zephyr-latest/drivers/adc/
Dadc_sam_afec.c36 #define NUM_CHANNELS 12 macro
201 (channels & (~0UL << NUM_CHANNELS))) { in start_read()
286 for (int i = 0; i < NUM_CHANNELS; i++) { in adc_sam_init()