Searched refs:NPCX_RESET_SWRST_CTL1_OFFSET (Results 1 – 3 of 3) sorted by relevance
10 #define NPCX_RESET_SWRST_CTL1_OFFSET 0 macro14 #define NPCX_RESET_GPIO0 (NPCX_RESET_SWRST_CTL1_OFFSET + 0)15 #define NPCX_RESET_GPIO1 (NPCX_RESET_SWRST_CTL1_OFFSET + 1)16 #define NPCX_RESET_GPIO2 (NPCX_RESET_SWRST_CTL1_OFFSET + 2)17 #define NPCX_RESET_GPIO3 (NPCX_RESET_SWRST_CTL1_OFFSET + 3)18 #define NPCX_RESET_GPIO4 (NPCX_RESET_SWRST_CTL1_OFFSET + 4)19 #define NPCX_RESET_GPIO5 (NPCX_RESET_SWRST_CTL1_OFFSET + 5)20 #define NPCX_RESET_GPIO6 (NPCX_RESET_SWRST_CTL1_OFFSET + 6)21 #define NPCX_RESET_GPIO7 (NPCX_RESET_SWRST_CTL1_OFFSET + 7)22 #define NPCX_RESET_GPIO8 (NPCX_RESET_SWRST_CTL1_OFFSET + 8)[all …]
10 #define NPCX_RESET_SWRST_CTL1_OFFSET 0 macro15 #define NPCX_RESET_GPIO0 (NPCX_RESET_SWRST_CTL1_OFFSET + 0)16 #define NPCX_RESET_GPIO1 (NPCX_RESET_SWRST_CTL1_OFFSET + 1)17 #define NPCX_RESET_GPIO2 (NPCX_RESET_SWRST_CTL1_OFFSET + 2)18 #define NPCX_RESET_GPIO3 (NPCX_RESET_SWRST_CTL1_OFFSET + 3)19 #define NPCX_RESET_GPIO4 (NPCX_RESET_SWRST_CTL1_OFFSET + 4)20 #define NPCX_RESET_GPIO5 (NPCX_RESET_SWRST_CTL1_OFFSET + 5)21 #define NPCX_RESET_GPIO6 (NPCX_RESET_SWRST_CTL1_OFFSET + 6)22 #define NPCX_RESET_GPIO7 (NPCX_RESET_SWRST_CTL1_OFFSET + 7)23 #define NPCX_RESET_GPIO8 (NPCX_RESET_SWRST_CTL1_OFFSET + 8)[all …]
