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Searched refs:MT_P_RW_U_RW (Results 1 – 4 of 4) sorted by relevance

/Zephyr-latest/soc/intel/intel_socfpga/agilex5/
Dmmu_regions.c20 MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
30 MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
35 MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
40 MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
/Zephyr-latest/soc/rockchip/rk3568/
Dmmu_regions.c17 MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_NS),
22 MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_NS),
/Zephyr-latest/include/zephyr/arch/arm64/
Darm_mmu.h82 #define MT_P_RW_U_RW (MT_RW | MT_RW_AP_ELx | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER) macro
205 {MT_P_RW_U_RW})
/Zephyr-latest/arch/arm64/core/
Dmmu.c829 .attrs = MT_NORMAL_NC | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE },
1290 MT_P_RW_U_RW | MT_NORMAL); in map_thread_stack()