Searched refs:MPU_RASR_TEX_Pos (Results 1 – 4 of 4) sorted by relevance
12 | (7 << MPU_RASR_TEX_Pos) \21 | (5 << MPU_RASR_TEX_Pos) \28 | (5 << MPU_RASR_TEX_Pos) \36 | (2 << MPU_RASR_TEX_Pos)) \
13 | (7 << MPU_RASR_TEX_Pos) \22 | (5 << MPU_RASR_TEX_Pos) \29 | (5 << MPU_RASR_TEX_Pos) \37 | (2 << MPU_RASR_TEX_Pos)) \
23 #define MPU_RASR_TEX_Pos 3 macro24 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
58 #define NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE ((1 << MPU_RASR_TEX_Pos) | MPU_RASR_S_Msk)59 #define NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE (1 << MPU_RASR_TEX_Pos)61 ((1 << MPU_RASR_TEX_Pos) | MPU_RASR_C_Msk | MPU_RASR_B_Msk | MPU_RASR_S_Msk)63 ((1 << MPU_RASR_TEX_Pos) | MPU_RASR_C_Msk | MPU_RASR_B_Msk)64 #define DEVICE_NON_SHAREABLE (2 << MPU_RASR_TEX_Pos)
