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Searched refs:MMCM (Results 1 – 5 of 5) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_control_litex.h34 #define DRP_BASE DT_REG_ADDR_BY_IDX(MMCM, 0)
36 #define DRP_ADDR_RESET DT_REG_ADDR_BY_NAME(MMCM, drp_reset)
37 #define DRP_ADDR_LOCKED DT_REG_ADDR_BY_NAME(MMCM, drp_locked)
38 #define DRP_ADDR_READ DT_REG_ADDR_BY_NAME(MMCM, drp_read)
39 #define DRP_ADDR_WRITE DT_REG_ADDR_BY_NAME(MMCM, drp_write)
40 #define DRP_ADDR_DRDY DT_REG_ADDR_BY_NAME(MMCM, drp_drdy)
41 #define DRP_ADDR_ADR DT_REG_ADDR_BY_NAME(MMCM, drp_adr)
42 #define DRP_ADDR_DAT_W DT_REG_ADDR_BY_NAME(MMCM, drp_dat_w)
43 #define DRP_ADDR_DAT_R DT_REG_ADDR_BY_NAME(MMCM, drp_dat_r)
46 #define LOCK_TIMEOUT DT_PROP(MMCM, litex_lock_timeout)
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DKconfig.litex7 bool "LiteX MMCM clock control"
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dclock_control_litex.h25 #define MMCM DT_NODELABEL(clock0) macro
26 #define NCLKOUT DT_PROP_LEN(MMCM, clock_output_names)
/Zephyr-latest/samples/drivers/clock_control_litex/
DREADME.rst11 The driver uses Mixed Mode Clock Manager (MMCM) module to generate up to 7 clocks with defined phas…
15 * LiteX-capable FPGA platform with MMCM modules (for example Digilent Arty A7 development board)
16 * SoC configuration with VexRiscv soft CPU and Xilinx 7-series MMCM interface in LiteX (S7MMCM modu…
63 dev = DEVICE_DT_GET(MMCM);
/Zephyr-latest/samples/drivers/clock_control_litex/src/
Dmain.c314 const struct device *const dev = DEVICE_DT_GET(MMCM); in main()