Searched refs:MINTSET (Results 1 – 4 of 4) sorted by relevance
339 uint32_t intmask = inst->MINTSET; in npcx_i3c_interrupt_all_disable()346 inst->MINTSET = mask; in npcx_i3c_interrupt_enable()363 inst->MINTSET |= BIT(NPCX_I3C_MINTSET_NOWCNTLR); /* I3C target is now controller */ in npcx_i3c_enable_target_interrupt()843 i3c_inst->MINTSET |= BIT(NPCX_I3C_MINTCLR_COMPLETE); /* Enable I3C complete interrupt */ in npcx_i3c_xfer_write_fifo_dma()1149 intmask = inst->MINTSET; in npcx_i3c_transfer()1334 intmask = inst->MINTSET; in npcx_i3c_do_daa()1505 intmask = inst->MINTSET; in npcx_i3c_do_ccc()1721 inst->MINTSET = BIT(NPCX_I3C_MINTSET_TGTSTART); in npcx_i3c_ibi_work()1866 inst->MINTSET = BIT(NPCX_I3C_MINTSET_TGTSTART); in npcx_i3c_ibi_enable()1918 inst->MINTSET = BIT(NPCX_I3C_MINTSET_TGTSTART); in npcx_i3c_ibi_disable()[all …]
209 uint32_t intmask = base->MINTSET; in mcux_i3c_interrupt_disable()225 base->MINTSET = mask; in mcux_i3c_interrupt_enable()1587 base->MINTSET = I3C_MINTSET_SLVSTART_MASK; in mcux_i3c_ibi_work()1733 base->MINTSET = I3C_MINTSET_SLVSTART_MASK; in mcux_i3c_ibi_enable()1787 base->MINTSET = I3C_MINTSET_SLVSTART_MASK; in mcux_i3c_ibi_disable()1827 base->MINTSET = I3C_MINTCLR_SLVSTART_MASK; in mcux_i3c_isr()
206 NPCX_REG_OFFSET_CHECK(i3c_reg, MINTSET, 0x090);
1869 volatile uint32_t MINTSET; member
