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Searched refs:MII_BMCR (Results 1 – 9 of 9) sorted by relevance

/Zephyr-latest/drivers/ethernet/
Dphy_gecko.c116 retval = phy_write(phy, MII_BMCR, MII_BMCR_RESET); in phy_soft_reset()
132 retval = phy_read(phy, MII_BMCR, &phy_reg); in phy_soft_reset()
211 retval = phy_read(phy, MII_BMCR, &val); in phy_gecko_auto_negotiate()
219 retval = phy_write(phy, MII_BMCR, val); in phy_gecko_auto_negotiate()
Deth_numaker.c101 mdio_write(gmacdev, eth_phy_addr, MII_BMCR, BMCR_RESET); in reset_phy()
104 ret = WAIT_FOR(!(mdio_read(gmacdev, eth_phy_addr, MII_BMCR) & BMCR_RESET), in reset_phy()
125 reg = mdio_read(gmacdev, eth_phy_addr, MII_BMCR); in reset_phy()
126 mdio_write(gmacdev, eth_phy_addr, MII_BMCR, reg | BMCR_ANRESTART); in reset_phy()
/Zephyr-latest/drivers/ethernet/phy/
Dphy_mii.c100 if (phy_mii_reg_write(dev, MII_BMCR, MII_BMCR_RESET) < 0) { in reset()
115 if (phy_mii_reg_read(dev, MII_BMCR, &value) < 0) { in reset()
187 if (phy_mii_reg_read(dev, MII_BMCR, &bmcr_reg) < 0) { in update_link_state()
194 if (phy_mii_reg_write(dev, MII_BMCR, bmcr_reg) < 0) { in update_link_state()
326 if (phy_mii_reg_read(dev, MII_BMCR, &bmcr_reg) < 0) { in phy_mii_cfg_link()
384 if (phy_mii_reg_write(dev, MII_BMCR, bmcr_reg) < 0) { in phy_mii_cfg_link()
Dphy_qualcomm_ar8031.c266 if (qc_ar8031_read(dev, MII_BMCR, &bmcr_reg) < 0) { in qc_ar8031_cfg_link()
320 if (qc_ar8031_write(dev, MII_BMCR, bmcr_reg) < 0) { in qc_ar8031_cfg_link()
384 ret = qc_ar8031_write(dev, MII_BMCR, MII_BMCR_RESET); in qc_ar8031_init()
455 ret = qc_ar8031_read(dev, MII_BMCR, &reg_value); in qc_ar8031_init()
460 ret = qc_ar8031_write(dev, MII_BMCR, reg_value); in qc_ar8031_init()
Dphy_realtek_rtl8211f.c145 ret = phy_rt_rtl8211f_write(dev, MII_BMCR, MII_BMCR_RESET); in phy_rt_rtl8211f_reset()
156 ret = phy_rt_rtl8211f_read(dev, MII_BMCR, &reg_val); in phy_rt_rtl8211f_reset()
185 ret = phy_rt_rtl8211f_read(dev, MII_BMCR, &bmcr); in phy_rt_rtl8211f_restart_autonegotiation()
195 ret = phy_rt_rtl8211f_write(dev, MII_BMCR, bmcr); in phy_rt_rtl8211f_restart_autonegotiation()
Dphy_microchip_ksz8081.c102 ret = phy_mc_ksz8081_read(dev, MII_BMCR, &bmcr); in phy_mc_ksz8081_autonegotiate()
113 ret = phy_mc_ksz8081_write(dev, MII_BMCR, bmcr); in phy_mc_ksz8081_autonegotiate()
308 ret = phy_mc_ksz8081_write(dev, MII_BMCR, MII_BMCR_RESET); in phy_mc_ksz8081_reset()
Dphy_ti_dp83825.c142 ret = phy_ti_dp83825_read(dev, MII_BMCR, &bmcr); in phy_ti_dp83825_autonegotiate()
153 ret = phy_ti_dp83825_write(dev, MII_BMCR, bmcr); in phy_ti_dp83825_autonegotiate()
345 ret = phy_ti_dp83825_write(dev, MII_BMCR, MII_BMCR_RESET); in phy_ti_dp83825_reset()
Dphy_adin2111.c367 ret = phy_adin2111_c22_write(dev, MII_BMCR, MII_BMCR_RESET); in phy_adin2111_reset()
/Zephyr-latest/include/zephyr/net/
Dmii.h26 #define MII_BMCR 0x0 macro