Searched refs:MDMA_CTL0 (Results 1 – 3 of 3) sorted by relevance
473 if (IS_BIT_SET(mdma_reg_base->MDMA_CTL0, NPCX_MDMA_CTL_MDMAEN)) { in uart_npcx_async_rx_dma_get_status()662 mdma_reg_base->MDMA_CTL0 |= BIT(NPCX_MDMA_CTL_MDMAEN) | BIT(NPCX_MDMA_CTL_SIEN); in uart_npcx_async_rx_enable()726 mdma_reg_base->MDMA_CTL0 &= ~BIT(NPCX_MDMA_CTL_MDMAEN); in uart_npcx_async_rx_disable()786 mdma_reg_base->MDMA_CTL0 |= BIT(NPCX_MDMA_CTL_MDMAEN) | BIT(NPCX_MDMA_CTL_SIEN); in uart_npcx_async_dma_load_new_rx_buf()860 if (IS_BIT_SET(mdma_reg_base->MDMA_CTL0, NPCX_MDMA_CTL_TC) && in uart_npcx_isr()861 IS_BIT_SET(mdma_reg_base->MDMA_CTL0, NPCX_MDMA_CTL_SIEN)) { in uart_npcx_isr()862 mdma_reg_base->MDMA_CTL0 &= ~BIT(NPCX_MDMA_CTL_SIEN); in uart_npcx_isr()864 mdma_reg_base->MDMA_CTL0 &= ~BIT(NPCX_MDMA_CTL_TC); in uart_npcx_isr()
905 mdma_inst->MDMA_CTL0 |= BIT(NPCX_MDMA_CTL_SIEN); /* Enable stop interrupt */ in npcx_i3c_xfer_read_fifo_dma()906 mdma_inst->MDMA_CTL0 |= BIT(NPCX_MDMA_CTL_MDMAEN); /* Start DMA transfer */ in npcx_i3c_xfer_read_fifo_dma()917 mdma_inst->MDMA_CTL0 &= ~BIT(NPCX_MDMA_CTL_SIEN); /* Disable stop interrupt */ in npcx_i3c_xfer_read_fifo_dma()2049 mdma_inst->MDMA_CTL0 &= ~BIT(NPCX_MDMA_CTL_MDMAEN); in npcx_i3c_target_disable_mdmafb()2050 mdma_inst->MDMA_CTL0 &= ~BIT(NPCX_MDMA_CTL_TC); /* W0C */ in npcx_i3c_target_disable_mdmafb()2051 mdma_inst->MDMA_CTL0 &= ~BIT(NPCX_MDMA_CTL_SIEN); in npcx_i3c_target_disable_mdmafb()2068 if (IS_BIT_SET(mdma_inst->MDMA_CTL0, NPCX_MDMA_CTL_MDMAEN) != 0) { in npcx_i3c_target_enable_mdmafb()2069 mdma_inst->MDMA_CTL0 &= ~BIT(NPCX_MDMA_CTL_MDMAEN); in npcx_i3c_target_enable_mdmafb()2083 mdma_inst->MDMA_CTL0 &= ~BIT(NPCX_MDMA_CTL_TC); /* W0C */ in npcx_i3c_target_enable_mdmafb()2084 mdma_inst->MDMA_CTL0 |= BIT(NPCX_MDMA_CTL_SIEN); /* Enable stop interrupt */ in npcx_i3c_target_enable_mdmafb()[all …]
2209 volatile uint32_t MDMA_CTL0; member
