1 /*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nxp_s32_mc_me
8
9 #include <zephyr/kernel.h>
10 #if defined(CONFIG_REBOOT)
11 #include <zephyr/sys/reboot.h>
12 #endif /* CONFIG_REBOOT */
13
14 /* Control Key Register */
15 #define MC_ME_CTL_KEY 0x0
16 #define MC_ME_CTL_KEY_KEY_MASK GENMASK(15, 0)
17 #define MC_ME_CTL_KEY_KEY(v) FIELD_PREP(MC_ME_CTL_KEY_KEY_MASK, (v))
18 /* Mode Configuration Register */
19 #define MC_ME_MODE_CONF 0x4
20 #define MC_ME_MODE_CONF_DEST_RST_MASK BIT(0)
21 #define MC_ME_MODE_CONF_DEST_RST(v) FIELD_PREP(MC_ME_MODE_CONF_DEST_RST_MASK, (v))
22 #define MC_ME_MODE_CONF_FUNC_RST_MASK BIT(1)
23 #define MC_ME_MODE_CONF_FUNC_RST(v) FIELD_PREP(MC_ME_MODE_CONF_FUNC_RST_MASK, (v))
24 #define MC_ME_MODE_CONF_STANDBY_MASK BIT(15)
25 #define MC_ME_MODE_CONF_STANDBY(v) FIELD_PREP(MC_ME_MODE_CONF_STANDBY_MASK, (v))
26 /* Mode Update Register */
27 #define MC_ME_MODE_UPD 0x8
28 #define MC_ME_MODE_UPD_MODE_UPD_MASK BIT(0)
29 #define MC_ME_MODE_UPD_MODE_UPD(v) FIELD_PREP(MC_ME_MODE_UPD_MODE_UPD_MASK, (v))
30 /* Mode Status Register */
31 #define MC_ME_MODE_STAT 0xc
32 #define MC_ME_MODE_STAT_PREV_MODE_MASK BIT(0)
33 #define MC_ME_MODE_STAT_PREV_MODE(v) FIELD_PREP(MC_ME_MODE_STAT_PREV_MODE_MASK, (v))
34 /* Main Core ID Register */
35 #define MC_ME_MAIN_COREID 0x10
36 #define MC_ME_MAIN_COREID_CIDX_MASK GENMASK(2, 0)
37 #define MC_ME_MAIN_COREID_CIDX(v) FIELD_PREP(MC_ME_MAIN_COREID_CIDX_MASK, (v))
38 #define MC_ME_MAIN_COREID_PIDX_MASK GENMASK(12, 8)
39 #define MC_ME_MAIN_COREID_PIDX(v) FIELD_PREP(MC_ME_MAIN_COREID_PIDX_MASK, (v))
40 /* Partition p Process Configuration Register */
41 #define MC_ME_PRTN_PCONF(p) (0x100 + 0x200 * (p))
42 #define MC_ME_PRTN_PCONF_PCE_MASK BIT(0)
43 #define MC_ME_PRTN_PCONF_PCE(v) FIELD_PREP(MC_ME_PRTN_PCONF_PCE_MASK, (v))
44 /* Partition p Process Update Register */
45 #define MC_ME_PRTN_PUPD(p) (0x104 + 0x200 * (p))
46 #define MC_ME_PRTN_PUPD_PCUD_MASK BIT(0)
47 #define MC_ME_PRTN_PUPD_PCUD(v) FIELD_PREP(MC_ME_PRTN_PUPD_PCUD_MASK, (v))
48 /* Partition p Status Register */
49 #define MC_ME_PRTN_STAT(p) (0x108 + 0x200 * (p))
50 #define MC_ME_PRTN_STAT_PCS_MASK BIT(0)
51 #define MC_ME_PRTN_STAT_PCS(v) FIELD_PREP(MC_ME_PRTN_STAT_PCS_MASK, (v))
52 /* Partition p COFB c Clock Status Register */
53 #define MC_ME_PRTN_COFB_STAT(p, c) (0x110 + 0x200 * (p) + 0x4 * (c))
54 /* Partition p COFB c Clock Enable Register */
55 #define MC_ME_PRTN_COFB_CLKEN(p, c) (0x130 + 0x200 * (p) + 0x4 * (c))
56 /* Partition p Core c Process Configuration Register */
57 #define MC_ME_PRTN_CORE_PCONF(p, c) (0x140 + 0x200 * (p) + 0x20 * (c))
58 #define MC_ME_PRTN_CORE_PCONF_CCE_MASK BIT(0)
59 #define MC_ME_PRTN_CORE_PCONF_CCE(v) FIELD_PREP(MC_ME_PRTN_CORE_PCONF_CCE_MASK, (v))
60 /* Partition n Core c Process Update Register */
61 #define MC_ME_PRTN_CORE_PUPD(p, c) (0x144 + 0x200 * (p) + 0x20 * (c))
62 #define MC_ME_PRTN_CORE_PUPD_CCUPD_MASK BIT(0)
63 #define MC_ME_PRTN_CORE_PUPD_CCUPD(v) FIELD_PREP(MC_ME_PRTN_CORE_PUPD_CCUPD_MASK, (v))
64 /* Partition n Core c Status Register */
65 #define MC_ME_PRTN_CORE_STAT(p, c) (0x148 + 0x200 * (p) + 0x20 * (c))
66 #define MC_ME_PRTN_CORE_STAT_CCS_MASK BIT(0)
67 #define MC_ME_PRTN_CORE_STAT_CCS(v) FIELD_PREP(MC_ME_PRTN_CORE_STAT_CCS_MASK, (v))
68 #define MC_ME_PRTN_CORE_STAT_WFI_MASK BIT(31)
69 #define MC_ME_PRTN_CORE_STAT_WFI(v) FIELD_PREP(MC_ME_PRTN_CORE_STAT_WFI_MASK, (v))
70 /* Partition n Core c Address Register */
71 #define MC_ME_PRTN_CORE_ADDR(p, c) (0x14c + 0x200 * (p) + 0x20 * (c))
72 #define MC_ME_PRTN_CORE_ADDR_ADDR_MASK GENMASK(31, 2)
73 #define MC_ME_PRTN_CORE_ADDR_ADDR(v) FIELD_PREP(MC_ME_PRTN_CORE_ADDR_ADDR_MASK, (v))
74
75 #define MC_ME_CTL_KEY_DIRECT_KEY 0x00005af0U
76 #define MC_ME_CTL_KEY_INVERTED_KEY 0x0000a50fU
77
78 /* Handy accessors */
79 #define REG_READ(r) sys_read32((mem_addr_t)(DT_INST_REG_ADDR(0) + (r)))
80 #define REG_WRITE(r, v) sys_write32((v), (mem_addr_t)(DT_INST_REG_ADDR(0) + (r)))
81
82 /** MC_ME power mode */
83 enum mc_me_power_mode {
84 /** Destructive Reset Mode */
85 MC_ME_DEST_RESET_MODE,
86 /** Functional Reset Mode */
87 MC_ME_FUNC_RESET_MODE,
88 };
89
90 #if defined(CONFIG_REBOOT)
mc_me_write_ctl_key(void)91 static inline void mc_me_write_ctl_key(void)
92 {
93 REG_WRITE(MC_ME_CTL_KEY, MC_ME_CTL_KEY_KEY(MC_ME_CTL_KEY_DIRECT_KEY));
94 REG_WRITE(MC_ME_CTL_KEY, MC_ME_CTL_KEY_KEY(MC_ME_CTL_KEY_INVERTED_KEY));
95 }
96
mc_me_trigger_mode_update(void)97 static inline void mc_me_trigger_mode_update(void)
98 {
99 REG_WRITE(MC_ME_MODE_UPD, MC_ME_MODE_UPD_MODE_UPD(1U));
100 mc_me_write_ctl_key();
101 }
102
mc_me_set_mode(enum mc_me_power_mode mode)103 static int mc_me_set_mode(enum mc_me_power_mode mode)
104 {
105 int err = 0;
106
107 switch (mode) {
108 case MC_ME_DEST_RESET_MODE:
109 REG_WRITE(MC_ME_MODE_CONF, MC_ME_MODE_CONF_DEST_RST(1U));
110 mc_me_trigger_mode_update();
111 break;
112 case MC_ME_FUNC_RESET_MODE:
113 REG_WRITE(MC_ME_MODE_CONF, MC_ME_MODE_CONF_FUNC_RST(1U));
114 mc_me_trigger_mode_update();
115 break;
116 default:
117 err = -ENOTSUP;
118 break;
119 }
120
121 return err;
122 }
123
124 /*
125 * Overrides default weak implementation of system reboot.
126 *
127 * SYS_REBOOT_COLD (Destructive Reset):
128 * - Leads most parts of the chip, except a few modules, to reset. SRAM content
129 * is lost after this reset event.
130 * - Flash is always reset, so an updated value of the option bits is reloaded
131 * in volatile registers outside of the Flash array.
132 * - Trimming is lost.
133 * - STCU is reset and configured BISTs are executed.
134 *
135 * SYS_REBOOT_WARM (Functional Reset):
136 * - Leads all the communication peripherals and cores to reset. The communication
137 * protocols' sanity is not guaranteed and they are assumed to be reinitialized
138 * after reset. The SRAM content, and the functionality of certain modules, is
139 * preserved across functional reset.
140 * - The volatile registers are not reset; in case of a reset event, the
141 * trimming is maintained.
142 * - No BISTs are executed after functional reset.
143 */
sys_arch_reboot(int type)144 void sys_arch_reboot(int type)
145 {
146 switch (type) {
147 case SYS_REBOOT_COLD:
148 mc_me_set_mode(MC_ME_DEST_RESET_MODE);
149 break;
150 case SYS_REBOOT_WARM:
151 mc_me_set_mode(MC_ME_FUNC_RESET_MODE);
152 break;
153 default:
154 /* Do nothing */
155 break;
156 }
157 }
158 #endif /* CONFIG_REBOOT */
159
