Searched refs:MCR20A_PHY_CTRL1_XCVSEQ_MASK (Results 1 – 2 of 2) sorted by relevance
438 if (((ctrl1 & MCR20A_PHY_CTRL1_XCVSEQ_MASK) == MCR20A_XCVSEQ_TX) || in mcr20a_abort_sequence()439 ((ctrl1 & MCR20A_PHY_CTRL1_XCVSEQ_MASK) == MCR20A_XCVSEQ_TX_RX)) { in mcr20a_abort_sequence()446 ctrl1 &= ~MCR20A_PHY_CTRL1_XCVSEQ_MASK; in mcr20a_abort_sequence()469 ctrl1 &= ~MCR20A_PHY_CTRL1_XCVSEQ_MASK; in mcr20a_set_sequence()618 uint8_t seq = dregs[MCR20A_PHY_CTRL1] & MCR20A_PHY_CTRL1_XCVSEQ_MASK; in irqsts1_event()691 dregs[MCR20A_PHY_CTRL1] &= ~MCR20A_PHY_CTRL1_XCVSEQ_MASK; in irqsts1_event()716 dregs[MCR20A_PHY_CTRL1] &= ~MCR20A_PHY_CTRL1_XCVSEQ_MASK; in irqsts3_event()779 ctrl1 &= ~MCR20A_PHY_CTRL1_XCVSEQ_MASK; in mcr20a_thread_main()
156 #define MCR20A_PHY_CTRL1_XCVSEQ_MASK (0x7) macro
