Searched refs:MCLKD_SL (Results 1 – 2 of 2) sorted by relevance
110 #define MCLKD_SL 2 /* I3C_CLK = (MCLK / 3) */ macro112 #define MCLKD_SL 1 /* I3C_CLK = (MCLK / 2) */ macro114 #define MCLKD_SL 0 /* I3C_CLK = MCLK */ macro172 #define VAL_HFCBCD3 MCLKD_SL
109 *rate = OFMCLK/(MCLKD_SL + 1); in npcx_clock_control_get_subsys_rate()193 BUILD_ASSERT(OFMCLK / (MCLKD_SL + 1) <= MHZ(50) &&194 OFMCLK / (MCLKD_SL + 1) >= MHZ(40),
