Home
last modified time | relevance | path

Searched refs:LFCLK (Results 1 – 10 of 10) sorted by relevance

/Zephyr-latest/drivers/clock_control/
DKconfig.npcx16 bool "Generate LFCLK by on-chip Crystal Oscillator"
18 When this option is enabled, the internal 32.768 KHz clock (LFCLK)
Dclock_control_npcm.c108 #define LFCLK 32768 macro
283 *rate = LFCLK; in npcm_clock_control_get_subsys_rate()
Dclock_control_npcx.c103 *rate = LFCLK; in npcx_clock_control_get_subsys_rate()
/Zephyr-latest/samples/boards/nordic/clock_skew/
DREADME.rst10 skew between HFCLK (used for the CPU) and LFCLK (used for system time).
12 LFCLK domain to durations in the HFCLK domain.
44 Power-up clocks: LFCLK[ON]: Running LFXO ; HFCLK[OFF]: Running HFINT
46 Timer-running clocks: LFCLK[ON]: Running LFXO ; HFCLK[OFF]: Running HFINT
/Zephyr-latest/drivers/sensor/nuvoton/nuvoton_tach_npcx/
Dtach_nuvoton_npcx.c112 SET_FIELD(inst->TCKC, NPCX_TCKC_C1CSEL_FIELD, data->input_clk == LFCLK in tach_npcx_start_port_a()
136 SET_FIELD(inst->TCKC, NPCX_TCKC_C2CSEL_FIELD, data->input_clk == LFCLK in tach_npcx_start_port_b()
229 } else if (data->input_clk == LFCLK) { in tach_npcx_configure()
/Zephyr-latest/soc/nuvoton/npcx/common/
Dsoc_clock.h74 #define LFCLK 32768 macro
/Zephyr-latest/boards/nuvoton/npcx7m6fb_evb/
Dnpcx7m6fb_evb.dts87 sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
/Zephyr-latest/boards/nuvoton/npcx9m6f_evb/
Dnpcx9m6f_evb.dts99 sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
/Zephyr-latest/drivers/watchdog/
Dwdt_npcx.c46 #define NPCX_WDT_CLK LFCLK
/Zephyr-latest/drivers/timer/
Dnpcx_itim_timer.c51 #define EVT_CYCLES_PER_SEC LFCLK /* 32768 Hz */