1 /* LAN9250 Stand-alone Ethernet Controller with SPI 2 * 3 * Copyright (c) 2024 Mario Paja 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #include <zephyr/kernel.h> 9 #include <zephyr/drivers/gpio.h> 10 #include <zephyr/drivers/spi.h> 11 12 #ifndef _LAN9250_ 13 #define _LAN9250_ 14 15 #define LAN9250_DEFAULT_NUMOF_RETRIES 3U 16 #define LAN9250_PHY_TIMEOUT 2000 17 #define LAN9250_MAC_TIMEOUT 2000 18 #define LAN9250_RESET_TIMEOUT 5000 19 20 #define LAN9250_ALIGN(v) (((v) + 3) & (~3)) 21 22 /* SPI instructions */ 23 #define LAN9250_SPI_INSTR_WRITE 0x02 24 #define LAN9250_SPI_INSTR_READ 0x03 25 26 /* TX command 'A' format */ 27 #define LAN9250_TX_CMD_A_INT_ON_COMP 0x80000000 28 #define LAN9250_TX_CMD_A_BUFFER_ALIGN_4B 0x00000000 29 #define LAN9250_TX_CMD_A_START_OFFSET_0B 0x00000000 30 #define LAN9250_TX_CMD_A_FIRST_SEG 0x00002000 31 #define LAN9250_TX_CMD_A_LAST_SEG 0x00001000 32 33 /* TX command 'B' format */ 34 #define LAN9250_TX_CMD_B_PACKET_TAG 0xFFFF0000 35 36 /* RX status format */ 37 #define LAN9250_RX_STS_PACKET_LEN 0x3FFF0000 38 39 /* LAN9250 System registers */ 40 #define LAN9250_RX_DATA_FIFO 0x0000 41 #define LAN9250_TX_DATA_FIFO 0x0020 42 #define LAN9250_RX_STATUS_FIFO 0x0040 43 #define LAN9250_TX_STATUS_FIFO 0x0048 44 #define LAN9250_ID_REV 0x0050 45 #define LAN9250_IRQ_CFG 0x0054 46 #define LAN9250_INT_STS 0x0058 47 #define LAN9250_INT_EN 0x005C 48 #define LAN9250_BYTE_TEST 0x0064 49 #define LAN9250_FIFO_INT 0x0068 50 #define LAN9250_RX_CFG 0x006C 51 #define LAN9250_TX_CFG 0x0070 52 #define LAN9250_HW_CFG 0x0074 53 #define LAN9250_RX_FIFO_INF 0x007C 54 #define LAN9250_TX_FIFO_INF 0x0080 55 #define LAN9250_PMT_CTRL 0x0084 56 #define LAN9250_MAC_CSR_CMD 0x00A4 57 #define LAN9250_MAC_CSR_DATA 0x00A8 58 #define LAN9250_AFC_CFG 0x00AC 59 #define LAN9250_RESET_CTL 0x01F8 60 61 /* LAN9250 Host MAC registers */ 62 #define LAN9250_HMAC_CR 0x01 63 #define LAN9250_HMAC_ADDRH 0x02 64 #define LAN9250_HMAC_ADDRL 0x03 65 #define LAN9250_HMAC_MII_ACC 0x06 66 #define LAN9250_HMAC_MII_DATA 0x07 67 68 /* LAN9250 PHY registers */ 69 #define LAN9250_PHY_BASIC_CONTROL 0x00 70 #define LAN9250_PHY_AN_ADV 0x04 71 #define LAN9250_PHY_SPECIAL_MODES 0x12 72 #define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND 0x1B 73 #define LAN9250_PHY_INTERRUPT_SOURCE 0x1D 74 #define LAN9250_PHY_INTERRUPT_MASK 0x1E 75 #define LAN9250_PHY_SPECIAL_CONTROL_STATUS 0x1F 76 77 /* Interrupt Configuration register */ 78 #define LAN9250_IRQ_CFG_INT_DEAS 0xFF000000 79 #define LAN9250_IRQ_CFG_INT_DEAS_10US 0x01000000 80 #define LAN9250_IRQ_CFG_INT_DEAS_100US 0x0A000000 81 #define LAN9250_IRQ_CFG_INT_DEAS_1MS 0x64000000 82 #define LAN9250_IRQ_CFG_INT_DEAS_CLR 0x00004000 83 #define LAN9250_IRQ_CFG_INT_DEAS_STS 0x00002000 84 #define LAN9250_IRQ_CFG_IRQ_INT 0x00001000 85 #define LAN9250_IRQ_CFG_IRQ_EN 0x00000100 86 #define LAN9250_IRQ_CFG_IRQ_POL 0x00000010 87 #define LAN9250_IRQ_CFG_IRQ_POL_LOW 0x00000000 88 #define LAN9250_IRQ_CFG_IRQ_POL_HIGH 0x00000010 89 #define LAN9250_IRQ_CFG_IRQ_CLK_SELECT 0x00000002 90 #define LAN9250_IRQ_CFG_IRQ_TYPE 0x00000001 91 #define LAN9250_IRQ_CFG_IRQ_TYPE_OD 0x00000000 92 #define LAN9250_IRQ_CFG_IRQ_TYPE_PP 0x00000001 93 94 /* INTERRUPT STATUS REGISTER (INT_STS) */ 95 #define LAN9250_INT_STS_SW_INT 0x80000000 96 #define LAN9250_INT_STS_READY 0x40000000 97 #define LAN9250_INT_STS_1588_EVNT 0x20000000 98 #define LAN9250_INT_STS_PHY_INT 0x04000000 99 #define LAN9250_INT_STS_TXSTOP_INT 0x02000000 100 #define LAN9250_INT_STS_RXSTOP_INT 0x01000000 101 #define LAN9250_INT_STS_RXDFH_INT 0x00800000 102 #define LAN9250_INT_STS_TX_IOC 0x00200000 103 #define LAN9250_INT_STS_RXD_INT 0x00100000 104 #define LAN9250_INT_STS_GPT_INT 0x00080000 105 #define LAN9250_INT_STS_PME_INT 0x00020000 106 #define LAN9250_INT_STS_TXSO 0x00010000 107 #define LAN9250_INT_STS_RWT 0x00008000 108 #define LAN9250_INT_STS_RXE 0x00004000 109 #define LAN9250_INT_STS_TXE 0x00002000 110 #define LAN9250_INT_STS_GPIO 0x00001000 111 #define LAN9250_INT_STS_TDFO 0x00000400 112 #define LAN9250_INT_STS_TDFA 0x00000200 113 #define LAN9250_INT_STS_TSFF 0x00000100 114 #define LAN9250_INT_STS_TSFL 0x00000080 115 #define LAN9250_INT_STS_RXDF_INT 0x00000040 116 #define LAN9250_INT_STS_RSFF 0x00000010 117 #define LAN9250_INT_STS_RSFL 0x00000008 118 119 /* INTERRUPT ENABLE REGISTER (INT_EN) */ 120 #define LAN9250_INT_EN_SW_INT_EN 0x80000000 121 #define LAN9250_INT_EN_READY_EN 0x40000000 122 #define LAN9250_INT_EN_1588_EVNT_EN 0x20000000 123 #define LAN9250_INT_EN_PHY_INT_EN 0x04000000 124 #define LAN9250_INT_EN_TXSTOP_INT_EN 0x02000000 125 #define LAN9250_INT_EN_RXSTOP_INT_EN 0x01000000 126 #define LAN9250_INT_EN_RXDFH_INT_EN 0x00800000 127 #define LAN9250_INT_EN_TIOC_INT_EN 0x00200000 128 #define LAN9250_INT_EN_RXD_INT_EN 0x00100000 129 #define LAN9250_INT_EN_GPT_INT_EN 0x00080000 130 #define LAN9250_INT_EN_PME_INT_EN 0x00020000 131 #define LAN9250_INT_EN_TXSO_EN 0x00010000 132 #define LAN9250_INT_EN_RWT_INT_EN 0x00008000 133 #define LAN9250_INT_EN_RXE_INT_EN 0x00004000 134 #define LAN9250_INT_EN_TXE_INT_EN 0x00002000 135 #define LAN9250_INT_EN_GPIO_EN 0x00001000 136 #define LAN9250_INT_EN_TDFO_EN 0x00000400 137 #define LAN9250_INT_EN_TDFA_EN 0x00000200 138 #define LAN9250_INT_EN_TSFF_EN 0x00000100 139 #define LAN9250_INT_EN_TSFL_EN 0x00000080 140 #define LAN9250_INT_EN_RXDF_INT_EN 0x00000040 141 #define LAN9250_INT_EN_RSFF_EN 0x00000010 142 #define LAN9250_INT_EN_RSFL_EN 0x00000008 143 144 /* Byte Order Test register */ 145 #define LAN9250_BYTE_TEST_DEFAULT 0x87654321 146 #define BOTR_MASK 0xffffffff 147 148 /* FIFO Level Interrupt register */ 149 #define LAN9250_FIFO_INT_TX_DATA_AVAILABLE_LEVEL 0xFF000000 150 #define LAN9250_FIFO_INT_TX_STATUS_LEVEL 0x00FF0000 151 #define LAN9250_FIFO_INT_RX_STATUS_LEVEL 0x000000FF 152 153 /* TRANSMIT CONFIGURATION REGISTER (TX_CFG) */ 154 #define LAN9250_TX_CFG_TXS_DUMP 0x00008000 155 #define LAN9250_TX_CFG_TXD_DUMP 0x00004000 156 #define LAN9250_TX_CFG_TXSAO 0x00000004 157 #define LAN9250_TX_CFG_TX_ON 0x00000002 158 #define LAN9250_TX_CFG_STOP_TX 0x00000001 159 160 /* HARDWARE CONFIGURATION REGISTER (HW_CFG) */ 161 #define LAN9250_HW_CFG_DEVICE_READY 0x08000000 162 #define LAN9250_HW_CFG_AMDIX_EN_STRAP_STATE 0x02000000 163 #define LAN9250_HW_CFG_MBO 0x00100000 164 #define LAN9250_HW_CFG_TX_FIF_SZ 0x000F0000 165 #define LAN9250_HW_CFG_TX_FIF_SZ_2KB 0x00020000 166 #define LAN9250_HW_CFG_TX_FIF_SZ_3KB 0x00030000 167 #define LAN9250_HW_CFG_TX_FIF_SZ_4KB 0x00040000 168 #define LAN9250_HW_CFG_TX_FIF_SZ_5KB 0x00050000 169 #define LAN9250_HW_CFG_TX_FIF_SZ_6KB 0x00060000 170 #define LAN9250_HW_CFG_TX_FIF_SZ_7KB 0x00070000 171 #define LAN9250_HW_CFG_TX_FIF_SZ_8KB 0x00080000 172 #define LAN9250_HW_CFG_TX_FIF_SZ_9KB 0x00090000 173 #define LAN9250_HW_CFG_TX_FIF_SZ_10KB 0x000A0000 174 #define LAN9250_HW_CFG_TX_FIF_SZ_11KB 0x000B0000 175 #define LAN9250_HW_CFG_TX_FIF_SZ_12KB 0x000C0000 176 #define LAN9250_HW_CFG_TX_FIF_SZ_13KB 0x000D0000 177 #define LAN9250_HW_CFG_TX_FIF_SZ_14KB 0x000E0000 178 179 /* RX FIFO Information register */ 180 #define LAN9250_RX_FIFO_INF_RXSUSED 0x00FF0000 181 #define LAN9250_RX_FIFO_INF_RXDUSED 0x0000FFFF 182 183 /* TX FIFO Information register */ 184 #define LAN9250_TX_FIFO_INF_TXSUSED 0x00FF0000 185 #define LAN9250_TX_FIFO_INF_TXFREE 0x0000FFFF 186 187 /* Power Management Control Register (PMT_CTRL) */ 188 #define LAN9250_PMT_CTRL_PM_MODE 0xE0000000 189 #define LAN9250_PMT_CTRL_PM_SLEEP_EN 0x10000000 190 #define LAN9250_PMT_CTRL_PM_WAKE 0x08000000 191 #define LAN9250_PMT_CTRL_LED_DIS 0x04000000 192 #define LAN9250_PMT_CTRL_1588_DIS 0x02000000 193 #define LAN9250_PMT_CTRL_1588_TSU_DIS 0x00400000 194 #define LAN9250_PMT_CTRL_HMAC_DIS 0x00080000 195 #define LAN9250_PMT_CTRL_HMAC_SYS_ONLY_DIS 0x00040000 196 #define LAN9250_PMT_CTRL_ED_STS 0x00010000 197 #define LAN9250_PMT_CTRL_ED_EN 0x00004000 198 #define LAN9250_PMT_CTRL_WOL_EN 0x00000200 199 #define LAN9250_PMT_CTRL_PME_TYPE 0x00000040 200 #define LAN9250_PMT_CTRL_WOL_STS 0x00000020 201 #define LAN9250_PMT_CTRL_PME_IND 0x00000008 202 #define LAN9250_PMT_CTRL_PME_POL 0x00000004 203 #define LAN9250_PMT_CTRL_PME_EN 0x00000002 204 #define LAN9250_PMT_CTRL_READY 0x00000001 205 206 /* HOST MAC CSR INTERFACE COMMAND REGISTER (MAC_CSR_CMD) */ 207 #define LAN9250_MAC_CSR_CMD_BUSY 0x80000000 208 #define LAN9250_MAC_CSR_CMD_WRITE 0x00000000 209 #define LAN9250_MAC_CSR_CMD_READ 0x40000000 210 #define LAN9250_MAC_CSR_CMD_ADDR 0x000000FF 211 212 /* Reset Control Register (RESET_CTL) */ 213 #define LAN9250_RESET_CTL_HMAC_RST 0x00000020 214 #define LAN9250_RESET_CTL_PHY_RST 0x00000002 215 #define LAN9250_RESET_CTL_DIGITAL_RST 0x00000001 216 217 /* HOST MAC CONTROL REGISTER (HMAC_CR) */ 218 #define LAN9250_HMAC_CR_RXALL 0x80000000 219 #define LAN9250_HMAC_CR_HMAC_EEE_ENABLE 0x02000000 220 #define LAN9250_HMAC_CR_RCVOWN 0x00800000 221 #define LAN9250_HMAC_CR_LOOPBK 0x00200000 222 #define LAN9250_HMAC_CR_FDPX 0x00100000 223 #define LAN9250_HMAC_CR_MCPAS 0x00080000 224 #define LAN9250_HMAC_CR_PRMS 0x00040000 225 #define LAN9250_HMAC_CR_INVFILT 0x00020000 226 #define LAN9250_HMAC_CR_PASSBAD 0x00010000 227 #define LAN9250_HMAC_CR_HO 0x00008000 228 #define LAN9250_HMAC_CR_HPFILT 0x00002000 229 #define LAN9250_HMAC_CR_BCAST 0x00000800 230 #define LAN9250_HMAC_CR_DISRTY 0x00000400 231 #define LAN9250_HMAC_CR_PADSTR 0x00000100 232 #define LAN9250_HMAC_CR_BOLMT 0x000000C0 233 #define LAN9250_HMAC_CR_BOLMT_10_BITS 0x00000000 234 #define LAN9250_HMAC_CR_BOLMT_8_BITS 0x00000040 235 #define LAN9250_HMAC_CR_BOLMT_4_BITS 0x00000080 236 #define LAN9250_HMAC_CR_BOLMT_1_BIT 0x000000C0 237 #define LAN9250_HMAC_CR_DFCHK 0x00000020 238 #define LAN9250_HMAC_CR_TXEN 0x00000008 239 #define LAN9250_HMAC_CR_RXEN 0x00000004 240 241 /* HOST MAC MII ACCESS REGISTER (HMAC_MII_ACC) */ 242 #define LAN9250_HMAC_MII_ACC_PHY_ADDR 0x0000F800 243 #define LAN9250_HMAC_MII_ACC_PHY_ADDR_DEFAULT 0x00000800 244 #define LAN9250_HMAC_MII_ACC_MIIRINDA 0x000007C0 245 #define LAN9250_HMAC_MII_ACC_MIIW_R 0x00000002 246 #define LAN9250_HMAC_MII_ACC_MIIBZY 0x00000001 247 248 /* PHY Basic Control Register (PHY_BASIC_CONTROL) */ 249 #define LAN9250_PHY_BASIC_CONTROL_PHY_SRST 0x8000 250 #define LAN9250_PHY_BASIC_CONTROL_PHY_LOOPBACK 0x4000 251 #define LAN9250_PHY_BASIC_CONTROL_PHY_SPEED_SEL_LSB 0x2000 252 #define LAN9250_PHY_BASIC_CONTROL_PHY_AN 0x1000 253 #define LAN9250_PHY_BASIC_CONTROL_PHY_PWR_DWN 0x0800 254 #define LAN9250_PHY_BASIC_CONTROL_PHY_RST_AN 0x0200 255 #define LAN9250_PHY_BASIC_CONTROL_PHY_DUPLEX 0x0100 256 #define LAN9250_PHY_BASIC_CONTROL_PHY_COL_TEST 0x0080 257 258 /* PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV) */ 259 #define LAN9250_PHY_AN_ADV_NEXT_PAGE 0x8000 260 #define LAN9250_PHY_AN_ADV_REMOTE_FAULT 0x2000 261 #define LAN9250_PHY_AN_ADV_EXTENDED_NEXT_PAGE 0x1000 262 #define LAN9250_PHY_AN_ADV_ASYM_PAUSE 0x0800 263 #define LAN9250_PHY_AN_ADV_SYM_PAUSE 0x0400 264 #define LAN9250_PHY_AN_ADV_100BTX_FD 0x0100 265 #define LAN9250_PHY_AN_ADV_100BTX_HD 0x0080 266 #define LAN9250_PHY_AN_ADV_10BT_FD 0x0040 267 #define LAN9250_PHY_AN_ADV_10BT_HD 0x0020 268 #define LAN9250_PHY_AN_ADV_SELECTOR 0x001F 269 #define LAN9250_PHY_AN_ADV_SELECTOR_DEFAULT 0x0001 270 271 /* PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS) */ 272 #define LAN9250_PHY_MODE_CONTROL_STATUS_EDPWRDOWN 0x2000 273 #define LAN9250_PHY_MODE_CONTROL_STATUS_ALTINT 0x0040 274 #define LAN9250_PHY_MODE_CONTROL_STATUS_ENERGYON 0x0002 275 276 /* PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND) */ 277 #define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_AMDIXCTRL 0x8000 278 #define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_AMDIXEN 0x4000 279 #define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_AMDIXSTATE 0x2000 280 #define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_SQEOFF 0x0800 281 #define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_FEFI_EN 0x0020 282 #define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_XPOL 0x0010 283 284 /* PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE) */ 285 #define LAN9250_PHY_INTERRUPT_SOURCE_LINK_UP 0x0200 286 #define LAN9250_PHY_INTERRUPT_SOURCE_ENERGYON 0x0080 287 #define LAN9250_PHY_INTERRUPT_SOURCE_AN_COMPLETE 0x0040 288 #define LAN9250_PHY_INTERRUPT_SOURCE_REMOTE_FAULT 0x0020 289 #define LAN9250_PHY_INTERRUPT_SOURCE_LINK_DOWN 0x0010 290 #define LAN9250_PHY_INTERRUPT_SOURCE_AN_LP_ACK 0x0008 291 #define LAN9250_PHY_INTERRUPT_SOURCE_PARALLEL_DETECT_FAULT 0x0004 292 #define LAN9250_PHY_INTERRUPT_SOURCE_AN_PAGE_RECEIVED 0x0002 293 294 /* PHY Interrupt Mask Register (PHY_INTERRUPT_MASK) */ 295 #define LAN9250_PHY_INTERRUPT_MASK_LINK_UP 0x0200 296 #define LAN9250_PHY_INTERRUPT_MASK_ENERGYON 0x0080 297 #define LAN9250_PHY_INTERRUPT_MASK_AN_COMPLETE 0x0040 298 #define LAN9250_PHY_INTERRUPT_MASK_REMOTE_FAULT 0x0020 299 #define LAN9250_PHY_INTERRUPT_MASK_LINK_DOWN 0x0010 300 #define LAN9250_PHY_INTERRUPT_MASK_AN_LP_ACK 0x0008 301 #define LAN9250_PHY_INTERRUPT_MASK_PARALLEL_DETECT_FAULT 0x0004 302 #define LAN9250_PHY_INTERRUPT_MASK_AN_PAGE_RECEIVED 0x0002 303 304 /* Chip ID and Revision register */ 305 #define LAN9250_ID_REV_CHIP_ID 0xFFFF0000 306 #define LAN9250_ID_REV_CHIP_ID_DEFAULT 0x92500000 307 #define LAN9250_ID_REV_CHIP_REV 0x0000FFFF 308 309 struct lan9250_config { 310 struct spi_dt_spec spi; 311 struct gpio_dt_spec interrupt; 312 struct gpio_dt_spec reset; 313 uint8_t full_duplex; 314 int32_t timeout; 315 }; 316 317 struct lan9250_runtime { 318 struct net_if *iface; 319 const struct device *dev; 320 321 K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_ETH_LAN9250_RX_THREAD_STACK_SIZE); 322 k_tid_t tid_int; 323 struct k_thread thread; 324 325 uint8_t mac_address[6]; 326 struct gpio_callback gpio_cb; 327 struct k_sem tx_rx_sem; 328 struct k_sem int_sem; 329 uint8_t buf[NET_ETH_MAX_FRAME_SIZE]; 330 struct k_mutex lock; 331 }; 332 333 #endif /*_LAN9250_*/ 334
