Searched refs:ISR_TX_FIFO_EMPTY (Results 1 – 2 of 2) sorted by relevance
54 (ISR_ADDR_TARGET | ISR_NOT_ADDR_TARGET | ISR_RX_FIFO_FULL | ISR_TX_FIFO_EMPTY | \150 *ints_to_clear |= ISR_TX_FIFO_EMPTY | ISR_TX_ERR_TARGET_COMP; in i2c_xilinx_axi_target_isr()151 *int_enable |= ISR_TX_FIFO_EMPTY | ISR_TX_ERR_TARGET_COMP; in i2c_xilinx_axi_target_isr()201 *int_enable &= ~ISR_TX_FIFO_EMPTY; in i2c_xilinx_axi_target_isr()202 *ints_to_clear |= ISR_TX_FIFO_EMPTY; in i2c_xilinx_axi_target_isr()203 } else if (data->target_reading && (*int_status & ISR_TX_FIFO_EMPTY)) { in i2c_xilinx_axi_target_isr()204 *int_status &= ~ISR_TX_FIFO_EMPTY; in i2c_xilinx_axi_target_isr()446 const uint32_t finish_bits = ISR_BUS_NOT_BUSY | ISR_TX_FIFO_EMPTY; in i2c_xilinx_axi_wait_tx_done()524 i2c_xilinx_axi_clear_interrupt(config, data, ISR_TX_FIFO_EMPTY | ISR_BUS_NOT_BUSY); in i2c_xilinx_axi_write()
53 ISR_TX_FIFO_EMPTY = BIT(2), /* Transmit FIFO Empty */ enumerator
